Application skills/reliability analysis of microcontroller reset circuit

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Application skills/reliability analysis of microcontroller reset circuit [Copy link]

Abstract : This paper summarizes the four widely used single-chip reset circuits, establishes mathematical models for differential and integral reset circuits, and compares their reliability in use. It also introduces dedicated reset chips. Finally, it proposes the issues that should be paid attention to in the design of reset circuits and measures to improve anti-interference performance.
	Keywords : reset, crash, reliability
	At present, single-chip microcomputers have been widely used in home appliances, medical treatment, instrumentation, industrial automation, aerospace and other fields. The more popular types of single-chip microcomputers on the market mainly include 8051 series single-chip microcomputers from Intel, Atmel and Philip, M6800 series single-chip microcomputers from Motorola, MCS96 series single-chip microcomputers from Intel and PIC series single-chip microcomputers from Microchip. No matter which type of single-chip microcomputer the user uses, the design of the reset circuit of the single-chip microcomputer is always involved. The quality of the reset circuit design of the single-chip microcomputer directly affects the reliability of the entire system. Many users have encountered "freeze" and "program runaway" on site after designing the single-chip microcomputer system and successfully debugging it in the laboratory. This is mainly caused by the unreliable reset circuit design of the single-chip microcomputer. Figure 1 is an example of a single-chip microcomputer and a high-power LED eight-segment display sharing a power supply and using a differential reset circuit. In this case, the system sometimes has some unpredictable phenomena, such as "freeze" and "program runaway" without any rules. However, this phenomenon does not occur or rarely occurs when debugging with an emulator. As shown in Figure 2, another reset circuit is used for resetting the microcontroller. In the application of this circuit, users sometimes find that the microcontroller may not work properly when the power is turned on again within a short period of time after the power is turned off. These phenomena can be considered to be caused by improper design of the microcontroller reset circuit.
	So far, there are four main types of microcontroller reset circuits: (1) differential reset circuit; (2) integral reset circuit; (3) comparator reset circuit; (4) watchdog reset circuit. In addition, companies such as Maxim have also launched dedicated chips (MAX813L) specifically for reset.
	1 Mathematical model and reliability analysis of reset circuit
	1.1 Differential reset circuit
	The equivalent circuit of the differential reset circuit is shown in Figure 3. Take high-level reset as an example. The following equation is established:
	When the power is turned on, Us can be considered as a step signal, that is, U0 is the voltage value caused by the pull-down resistor R at the CPU reset terminal, which is generally below 0.3V. However, in actual applications, Us cannot be an ideal step signal. There are two main reasons: (1) the output switching characteristics of the voltage-stabilized power supply; (2) when designers design circuits, in order to ensure the stability of the power supply voltage, they often connect a large capacitor in parallel to the input end of the power supply, which makes Us impossible to be a step signal characteristic. Since the first case is essentially the same as the second case, that is, it affects the rising slope of Us, thereby affecting the reset characteristics of URST. For this reason, it is assumed that the rising slope of Us is k, and it takes T time from 0V to Us, that is:
	When T<<τ, Us can be equivalent to a step signal when it is powered on. Same as before, when T>>τ, let A=T/τ, then:
	That is, the reset reliability at this time is better than the previous one.
	Another situation is that the designer uses some switching power devices, such as high-power LEDs, to share a regulated power supply with the MCU system, and the reset end of the MCU system uses a differential reset circuit, which will also cause abnormal reset. The specific analysis is shown in Figure 4.
	The device is equivalent to a resistor RL, where the switch characteristic is that RL is very small or RL is very large. The basic working principle of the voltage-regulated power supply is: ΔRL→ΔI→ΔU→-ΔI→-ΔU. It can be seen that the change of load will inevitably lead to the change of current. For the sake of simplicity of analysis, it is assumed that R>RL, and R>>R0. In this way, the above circuit network can be approximately regarded as a combination of two networks, and the load effect between the networks can be ignored.
	The first circuit network is equivalent to a voltage divider circuit. When RL changes from RLmin→Rlmax, it changes to a step-like state, and UA is a step signal. UA(t)=[Rlmax/(Rlmax+R0)]U t≥0 UA(t)=[Rlmin/(Rlmin+R0)]U t<0 Using this step signal as the input of the second circuit network, the first-order differential circuit, the following formula can be obtained: (d/dt)UA(t)=(1/RC)URST(t)+(d/dt)URST(t) URST(0)=0 Solving it, we get:
	It can be seen from the above formula that due to the sudden change of load and the voltage regulation of the regulated power supply, a pulse-like state will be introduced at the reset terminal, causing the CPU to malfunction.
	2 Integral reset circuit
	The equivalent circuit of this circuit is shown in Figure 5. Still taking the high level reset as an example, the following equation can also be established:
	When the system is powered on, assuming that Us(t)=AU(t) is a step function and U0=0, then:
	When the inverter works normally, if Uc can still be kept below VIL, its output can be high level; and if Uc can reach above VIL after a time TR not less than the reset pulse width has passed since the inverter works normally, then the power-on reset can be guaranteed to be reliable. Therefore, in practical applications, designers often increase the values of R and CF to increase the time constant, and use CMOS inverters with Schmitt inputs to improve anti-interference. However, this reset circuit often malfunctions when the time interval of the secondary power switch is relatively short. This is mainly because the discharge circuit is the same as the charging circuit, resulting in a large discharge time constant, which causes the UC voltage to drop excessively. For this reason, the literature [2] introduces an improved circuit as shown in Figure 6.
	It can be seen from Figure 6 that the time constant of the discharge circuit is generally much smaller than the charging time constant. At this time, the phenomenon of unreliable power-on reset caused by repeated switching of the power supply mentioned above can be controlled. However, since the discharge time constant is too short, the insensitivity of this reset circuit to power supply voltage fluctuations during operation is reduced. For example, when the power supply voltage fluctuates, the discharge is too fast at this time, which may cause Uc to be lower than the VIL voltage value of the inverter, resulting in unnecessary reset pulses. This phenomenon may occur when the microcontroller switches between Sleep mode and Active mode, and the power supply output power is relatively weak. For this reason, an improved integral reset circuit (as shown in Figure 7) is proposed to address the above phenomenon. In Figure 7, R1<<R2, and the above situation can be avoided by properly adjusting the value of R1.
	1.3 Comparator type reset circuit
	The basic principle of the comparator reset circuit is shown in Figure 8. During power-on reset, since an RC low-pass network is formed, the voltage at the positive input of the comparator is delayed by a certain time compared to the negative input voltage. The time constant of the negative network of the comparator is much smaller than the time constant of the positive RC network. Therefore, when the positive voltage has not exceeded the negative voltage, the comparator outputs a low level and generates a high level after the inverter. The width of the reset pulse mainly depends on the speed of normal voltage rise. Since the time constant of the negative voltage discharge circuit is large, it is insensitive to power supply voltage fluctuations. However, the following two unfavorable phenomena are prone to occur: (1) When the secondary switching interval of the power supply is too short, the reset is unreliable; (2) When there is a surge in the power supply voltage, the reset pulse may not be generated after the surge disappears. For this reason, the comparator reset circuit will be improved, as shown in Figure 9.
	This improved circuit can eliminate the first phenomenon and reduce the occurrence of the second phenomenon. In order to completely eliminate these two phenomena, the digital logic method can be used in conjunction with the comparator to design a comparator reset circuit as shown in Figure 10. This circuit can be used as a circuit for resetting the power-on reset and the watchdog reset circuit with a slight improvement, greatly improving the reliability of the reset.
	1.4 Watchdog reset circuit
	The watchdog reset circuit mainly uses the CPU to reset the counter regularly when it is working normally, so that the counter value does not exceed a certain value; when the CPU cannot work normally, since the counter cannot be reset, its count will exceed a certain value, thereby generating a reset pulse, so that the CPU returns to normal working state. The typical application of the watchdog reset circuit is shown in Figure 11. The reliability of this reset circuit mainly depends on the software design, that is, where the program that sends pulses to the reset circuit regularly is placed. Generally, this program is placed in the timer interrupt service subroutine. However, sometimes this design still causes the program to run away or work abnormally [3]. The main reason is that when the program "runs away", after the timer is initialized and the interrupt is enabled, this "runaway" situation may not be corrected by the watchdog reset circuit. Because once the timer interrupt is actually generated, the watchdog can be reset normally even if the program is abnormal. For this reason, a timer preset design method is proposed. That is, an address is pushed into the stack during initialization, and a statement to disable the interrupt and an infinite loop is executed at this address. All addresses not occupied by program code are replaced with the subroutine return instruction RET as much as possible. In this way, when the program goes astray, the possibility of entering a trap will be greatly increased. Once entering the trap, the timer stops working and turns off the interrupt, so that the watchdog reset circuit will generate a reset pulse to reset the CPU. Of course, this technology has certain difficulties in using control or processing software with strong real-time requirements.
	2 Introduction to dedicated reset chip (MAX813L)
	At present, there are many popular dedicated reset chips on the market. Understanding their working principles is crucial for the analysis and design of circuit reliability. Taking the MAX813L produced by Maxim as an example, the general working principle of dedicated reset chips is dissected. For other chips, the conclusion can be drawn by analyzing them one by one according to the four reset circuits provided in this article.
	MAX813L has four functions: power-on reset, watchdog output, power-off voltage monitoring, and manual reset. The specific principle block diagram is shown in Figure 12. This article is limited to discussing the reset circuit part and the watchdog timer part. As can be seen from Figure 12, WDI (Watchdog Input) is mainly used to reset the watchdog counter. If the CPU does not trigger the reset watchdog timer within 1.6 seconds, WDO (Watchdog Output) will output a low level. The reset circuit is divided into manual reset and power-on reset. As can be seen from the schematic diagram 12, the power-on reset is the same as the circuit principle mentioned in Figure 10 of this article, that is, the comparator generates a trigger signal to trigger the trigger, thereby generating a reset signal. At the same time, the pulse generated by the time base is timed. When the reset time reaches 140 milliseconds, the Reset generator generates a pulse to invalidate the reset signal. During power-on reset, as long as the voltage is lower than 4.63V, the reset signal Reset is valid; when the power supply voltage exceeds 4.63V, the Reset signal will continue to be maintained for about 140 milliseconds to ensure that the CPU reset is reliable and then invalid. During manual reset, if the MR (Manual Reset) grounding time is not less than 150 nanoseconds, a manual reset process can be generated. That is, a valid reset signal (high level is valid) of 140 milliseconds is generated at the reset end. If the WDO end is connected to MR, a power-on reset and watchdog reset circuit can be formed.
	3. Notes on reset circuit design
	Among the various reset circuits mentioned in this article, the differential reset circuit is simple, but it is easy to introduce interference and has no ability to monitor the CPU operation; the integral reset circuit is simple and reliable, but because it is not sensitive to power supply voltage fluctuations, it is possible that the CPU may malfunction due to the momentary low power supply voltage; the comparator reset circuit is more complex and reliable; the watchdog reset circuit is more complex, reliable and has the ability to monitor the CPU operation. In use, it should be comprehensively considered based on the space of the circuit board, the power supply voltage characteristics, the system operation site, etc. Generally, the following points can be used for reference:
	(1) When using a differential reset circuit and a regulated power supply, consider adding an appropriate inductor to the capacitor input to reduce the generation of interference reset pulses caused by sudden load changes. This reset circuit can be used when the circuit board space is limited.
	(2) When using an integral reset circuit, on the one hand, the rising rate of the power supply voltage during power-on reset should be considered. In particular, when the rising rate of the power supply voltage is small, a more complex comparison reset circuit should be considered. On the other hand, it should be considered whether the circuit has a voltage reduction measure to reduce power consumption. If so, the effect of the forward voltage drop of the diode on the reset circuit should be considered.
	(3) When designing a comparator reset circuit, the fluctuation of the power supply voltage should be considered. When the system works in a harsh environment, the intrusion of external interference may cause glitch voltage, resulting in abnormal reset. For this reason, it is necessary to take the following measures based on the peak-to-peak value of the glitch voltage and the pulse width: (a) When the peak-to-peak value of the glitch voltage does not reach the difference between the normal value of the power supply voltage and the minimum voltage value required for the normal operation of the system, the lower limit of the reset voltage of the comparator can be appropriately reduced; (b) When the peak-to-peak value of the glitch voltage exceeds the difference between the normal value of the power supply voltage and the voltage required for the normal operation of the system, on the one hand, measures should be taken to reduce the glitch voltage, and on the other hand, a more complex comparator type power-on reset circuit should be used (as shown in Figure 12).
	(4) When selecting or designing a watchdog reset circuit, you should note that the "feed dog" signal input to the watchdog should be an edge signal, not a level signal. At the same time, you should consider that the power supply voltage value for canceling the reset voltage should be greater than the minimum normal voltage value of the system.