Application of LAN91C111 controller in embedded Ethernet interface

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Application of LAN91C111 controller in embedded Ethernet interface [Copy link]

Abstract: Embedded Ethernet can not only be used in industrial sites to realize the automatic Internet access function of field nodes, but also can be used for the Ethernet interface of information appliances to realize remote control, which has a good development prospect. This article introduces the interface circuit and software and hardware implementation method of the embedded system based on TMS320LF2407 DSP and LAN91C111 adaptive 10Mb/s/100Mb/s embedded Ethernet control.

Keywords: Digital Signal Processing LAN91C111 TCP/IP Embedded Ethernet

1 Introduction

In the context of the increasing networking of electronic devices, the widely used Ethernet and TCP/IP protocols have become one of the most commonly used network standards. Its high speed, reliability, layering and scalability make it more and more flexible in various fields. In many cases, the use of Ethernet and TCP/IP can simplify the structure and reduce costs. At present, there are not many design schemes for embedded Ethernet, most of which are based on single-chip microcomputers, with the disadvantages of slow speed and high cost. As a special embedded microprocessor system, DSP has an embedded coprocessor and parallel data channels for fast data processing. The introduction of DSP technology in embedded network devices can make embedded Ethernet faster, cheaper and easier to expand functions. This article introduces the interface circuit and implementation method of the embedded system based on TMS320LF2407 and the LAN91C111 adaptive 10Mb/s/100Mb/s embedded Ethernet control chip.

2 LAN91C111

LAN91C111 is the third generation Fast Ethernet controller launched by SMSC for embedded application systems. The LAN91C111 chip integrates MAC (media layer) and PHY (physical layer) that follow the SMSC/CD protocol and complies with the IEEE802.3/802.U-100Base-Tx/10Base-T specification. Its system structure is shown in Figure 1. The main functions of this Ethernet controller are as follows:

Adaptively select transmission rate, support 10Mb/s/100Mb/s;

Fully support full-duplex switched Ethernet;

Support burst data transmission;

8k bytes of internal memory used as FIFO buffer for receiving and sending;

Enhanced energy management capabilities;

Support bus 8-bit, 16-bit, 32-bit CPU access;

Send and receive in advance.

The LAN91C111 Ethernet controller follows the 802.3 Ethernet transmission protocol promulgated by IEEE. Its 8-32-bit data bus interface unit is connected to the external CPU through the control bus, address bus and data bus. External data can be exchanged with the LAN91C111 in 8-bit, 16-bit or 32-bit mode. The circuit also integrates an EEPROM interface, which is input into the chip through the EEPROM interface during booting to achieve automatic initialization. The bus arbiter is used to monitor the data exchange of the Ethernet bus. Once a blockage occurs, the arbiter contacts the external CPU through the bus interface unit on the one hand, and controls the memory control unit (MMU) on the other hand to achieve bus data coordination. The memory control unit can control the storage of 8kB dynamic SRAM to achieve data communication with the DMA controller. The DMA controller and the bus controller together control the data exchange between the DMA and the Ethernet protocol processor (EPH). Data exchange between Ethernet protocol processors (EPH). The data from the Ethernet protocol processor finally reaches the Ethernet bus directly through the 10Mb/s/100Mb/s physical layer (PHY).

3 Hardware circuit composition

Considering the cost performance, the DSP controller is selected as the main CPU. TMS320LF2407 is a cost-effective DSP released by TI, suitable for the field of industrial control. This series has a powerful instruction system, strong flexibility, high-speed mathematical processing function and a brand-new internal structure, and can be widely used in communication, computer, business, industry, military and other fields. TMS320LF2407 is the most powerful one in the 240X series controller. It adopts low-power CMOS technology, has an execution rate of 30MI/s, and also integrates a wealth of peripheral components (EVM, A/D module, CAN, SCI, SPI and JTAG) on the chip. TMS320LF2407 has a high operating frequency (40MHz) and a large storage space (up to 32k words of FLASH program memory, can expand external 64k words of memory, 64k words of I/O addressing space), which is very suitable for processing complex TCP/IP protocols. Since LAN91C111 is designed for embedded systems, its peripheral circuits are relatively simple. The embedded Ethernet structure formed by it, a 16-bit DSP (TMS320LF2407) without DMA transmission performance and a TG110-S050N2 electromagnetic coupling transformer is shown in Figure 2. In the figure, the address bus A1-A15 is connected. A0 is not used by LAN91C111 and is suspended; the data bus D0-D15 is connected and used for 16-bit data transmission. The LAN91C111 end D16-D32 is suspended; the chip select signal AEN of LAN91C111 is provided by the external I/O interface selection signal IS of DSP. The read level RD and write level WR of the two components are connected respectively. The interrupt output signal INTRO of LAN91C111 is sent to the external interrupt pin XINT1 of DSP to trigger the interrupt. The circuit principle of the embedded Ethernet communication module is shown in Figure 3.

4 Software Design

4.1 Porting of μC/OS II Real-time Operating System

μC/OS II is an open source real-time embedded operating system. It is a portable, customizable, and curable preemptive multitasking operating system that has been applied to a variety of microprocessors. Most of its source code is written in ANSI C. The porting work includes the following:

(1) Rewrite the OS_CPU_A.ASM file in assembly language

The file includes 4 subroutines: _OSStartHighRdy, OSCtxSw, OSIntCtxSw and OSTickISR. The OSStartHighRdy() function is called by the OSStart() function, and its function is to run the ready task with the highest priority; the OSCtxSw() function is called by the OS Sched() function, and its function is to implement task switching at the task level, and task switching is implemented using soft interrupt No. 31; the OSIntCtxSw() function can only be called by the OSIntExit() function in the interrupt subroutine. Since the generation of an interrupt may cause a task switch, the OSIntExit() function will be called at the end of the interrupt service program. Since the generation of an interrupt may cause a task switch, the OSIntExit() function will be called at the end of the interrupt service program to check the task ready state. If the task switching conditions are met (in the last layer of interrupts, and a high-priority task is ready), OSIntExit() calls this function to implement task switching; the function of the clock beat function OSTickISR() is as follows: TMS320LF2407 has 4 general-purpose timers, and their interrupt priorities are T1, T3, T2, and T4 from high to low. One of the bases can be selected according to actual needs to implement the clock beat. It should be noted that the interrupt cannot be enabled before calling _OSIntEnter. If the interrupt is enabled before calling _OSIntEnter, it is possible that the interrupt will be triggered before OSIntNesting is incremented by 1. If this happens, when the high-priority interrupt exits by calling OSIntExit(), it should directly switch to the task from the high-priority interrupt instead of returning to _OSTickISR (assuming _OSTickISR is the last interrupt). The fundamental reason is that _OSTickISR is interrupted before it has time to increment OSIntNesting by 1. This type of error should also be prevented in other interrupt service routines of the user.

(2) Rewrite the OS CPU_C.C file in C language

This file only includes an OSTaskStkInit() subroutine. This function can imitate TI's 1$$SAVE library function to initialize the task stack, and is called by OSTaskCreate() and OSTaskCreateExt() functions. This function is used to return the pointer value of the initialized task stack. Note: The stack of TMS320LF2407A itself (hereinafter referred to as US) has only 8 levels and cannot be used as a system stack, so the C compiler reserves its two internal breakout points AR0 and AR1, of which AR1 is used as the stack pointer SP, and AR0 is used as the temporary variable pointer FP in the stack (do not use these two registers in the assembly program. If you must use them, turn off interrupts and pay attention to saving and restoring). The compiler pushes functions and interrupts into the return address of US, pops them out and places them on the stack of the SP (AR1) guide, and retains the environment. The difference is that functions only retain the registers to be used by the program, and interrupts call I$$AVE to save all registers. When returning, they jump to (rather than call) I$$REST (the source code of these two functions can be seen in RTS.SRC) to restore registers. These two functions are like the interrupt entry and instruction HRET in 8068, and are the basis for porting the OSTaskStkInit() function.

(3) Write OS_CPU.H file

The content can be modified according to the content of "80×86" in μC/OS-II. Only the key content is given here:

#define OS STK GROWTH 0

#define OS ENTER CRITICAL() asm("SETC IN TM");

#define OS_EXIT CRITICAL() asm ("CLRC IN TM");

#define OS-ASKee SW() asm("INTR 31");

(4) Appropriate OSMap Tb1[] and OSUnMapTb1[]

When porting, it is also necessary to properly process the two tables OSMapTb1[] and O-SunMapTb1[] of tic/OS-II, otherwise addressing errors will occur and μC/OS-II will not be able to operate normally. This is one of the important factors for the success of the porting. Since the memory of TMS320LF2407 adopts the Harvard structure, the Flash memory (or the external ROM) is located in the program area. Therefore, the processing method is as follows: change the data type of OSMapTb1[] and OSUnMapTb1[] in tic/OS-II from "INT8U const" to 'INT8U', and allocate the ".cinit" block to the Flash memory (or the external ROM in the linker command file (.CMD), and use the link option "-C" (ROM initialization). In this way, the RAM in the data area will be automatically initialized when the program is running, that is, the data in the ".cinit" block will be automatically copied to the RAM in the data area during operation.

After configuring OS-FG.H as needed and modifying the CPU interrupt vector table and peripheral vector table, the contents of other documents can be set accordingly according to actual needs. At this point, the porting of μC/OS-II on TMS320LF2407 is completed.

4.2 LAN91C111 Programming

4.2.1 Initialization

After power-on, the values of the internal registers of LAN91C111 are set to default values. The CPU will set the Configuration, Base and Individual Address registers as needed to ensure the correct operation of the circuit.

4.2.2 Data packet sending process

(1) The DSP sends an ALLOCATE MEMORY command to the controller (setting the MMUCOM register, usually set to 0x0020), and the MMU allocates storage space in the packet buffer inside the controller for the packet to be sent.

(2) DSP queries the ALLOC INT bit in the Interrupt Status register until it is set to 1. It can also set the ALLOC INT bit in the Interrupt Mask and then wait for the hardware interrupt. At this time, the MMU has allocated storage space. And the TX packet number is placed in the Allocation Result register. (3) Copy the packet number: in the Allocation Result register to the Packet Number: register and set the Pointer register (set to TX; WR, AUTOINC, i.e. 0x4000). Then transfer the data in the packet from the upper layer send queue to the controller's Data Register. It is required to write Status Word, Byte Count, destination address, source address, packet size, packet data, and control word in sequence.

(4) DSP sends the "ENQUEUE PACKET NUMBER TO TX FIFO" command to the controller (set the MMUCOM register, usually set to 0x00C0). This command copies the packet number in the Packet Number register to the TX FIFO, indicating that the transmitted packet has been placed in the queue. At the same time, the TXENA bit in the Transmit control register is set. At the same time, the TXENA bit in the Transmit control register is set to start the transmitter. So far, the DSP's setup work is completed, and it can be IDLE until it receives a transmit interrupt generated by the controller.

(5) After the controller transmits the packet, the first word (16 bits) in the memory is written to the corresponding Status Word by CSMA/CD, and then the packet number in the TX FIFO is moved to the TX completion FIFO. An interrupt is generated when the TX completion FIFO is not empty.

(6) After receiving the interrupt, the DSP starts to execute the interrupt handler. It reads the Interrupt Status register. If a transmit interrupt is generated, it reads the packet number in the transmitted packet from the FIFO ports register and writes it to the packet number register. Then it reads the Status Word from the memory (including setting the Pointer register to TX, RD, AUTOINC, i.e. 0x6000, and then reading the packet's Status Word from the data register), which is a mirror image of the EPH register. It then determines whether the packet is successfully transmitted based on the Status Word. If successful, the DSP sends a RELEASE command to the controller (setting the MMUCOM register to 0x00A0). The controller then releases the storage space used for the transmit packet and sets the TX INT Acknowledge register, which clears the packet unmber in the TX completion FIFO. There are two ways to generate a transmit interrupt: one interrupt is generated for each packet sent; one interrupt is generated for each sequence of packets sent. These two schemes are selected by the Auto Release bit of the Control register, and the transmit interrupt bits used by these two schemes are also different.

TX INT: set to 1e when the TX completion FIFO is not empty;

TX EMPTY INT: set to when the TX FIFO is empty;

AUTO RELEASE: If set to 1, after the packet is successfully sent, the packet number is not written to the TX completion FIFO, and the storage space it uses is automatically released.

Figure 3 (7) When using the "generate an interrupt for each packet sent" scheme, AUTO RELEASE=0, and the process of this scheme is as described above. When using the "generate an interrupt for each packet sent in a sequence" scheme, TX EMPTY INT and TX INT are allowed, AUTORELEASE=1, and a TX EMPTY INT interrupt is generated after the last packet in the FIFO is sent. If a serious transmission error occurs, a TX INT interrupt is generated, and the packet number of the failed packet is saved in the FIFO Ports register, so that the DSP can know that the transmission process has stopped. This scheme can reduce the burden on the DSP, and the storage space is released more quickly. When AUTO RELEASE=1, the DSP cannot obtain the packet number of the successfully transmitted packet.

4.2.3 Data packet receiving process

(1) The DSP sets the RXEN bit in the receive control register to allow packet reception.

(2) When a packet with the correct address is received, storage space is requested from the MMU and a packet number is assigned. The internal DMA logic generates continuous addresses and writes the received words to the memory. If the address exceeds the boundary, the packet is discarded and the storage space is released. When the end of the packet is detected, the Status Word is written to the front of the received packet and the byte count is written to the second word. If the CRC check is correct, the packet number is written to the RX FIFO. Since the RX FIFO is not empty, an RCV INT interrupt will be generated. If the RCR check is incorrect, the storage space is released and no interrupt is generated.

(3) After receiving the interrupt, the DSP starts to execute the interrupt processing program. First, it reads the Interrupt Status register. If a receive interrupt is generated (RCV INT bit is 1), the packet number of the received packet can be obtained from the FIFO ports register, and the received packet can be transferred to the DSP's internal memory or external memory from the data register. When the processing is completed, the DSP sends the REMOVE AND RELEASE FROM TOP OF RX command to the processor (that is, setting the register MMUCOM to 0x0060) to release the used storage space and packet number.

5 Conclusion

Ethernet has become the focus of the next generation of industrial control networks with its good versatility and outstanding bandwidth performance. This design uses the LAN91C111 embedded Ethernet controller and DSP to form an embedded Ethernet communication system. The system can correctly access Fast Ethernet and has multiple functions such as 100/10Mbit/s, full-duplex/half-duplex self-adaptation. It complies with IEEE802.3/802.3μ-100Base-TX/1Obase-T specifications. Its embedded Ethernet interface supports RJ45 and Ethernet connections, and can access the Internet through Ethernet, thereby realizing the monitoring of embedded devices from the Internet. The automatic negotiation mode of Ethernet and Fast Ethernet makes LAN91C111 very cost-effective and has a wide range of applications.