ADC Application Elements in C8051F020

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ADC Application Elements in C8051F020 [Copy link]

Abstract: This paper summarizes the application elements of the analog-to-digital conversion part in the SOC chip C8051F020, including accuracy and channel, rate and startup, reference and gain, data and control, and proposes the operating sequence of programming and related SFRs.

Keywords: System on Chip (SOC), A/D Converter (ADC), Special Function Register (SFR)

C8051F020 (F020 for short) is a mixed signal SOC type 8-bit single chip microcomputer launched by Cygnal Corporation in Texas, USA. It belongs to the F02x sub-series of the C8051F series. Its performance-price ratio is very competitive in the current application field. F020 has 8-channel 12-bit A/D conversion (ADC for short) interface and 8-channel 8-bit online programmable (ISP) ADC circuit. There are 15 special function registers (SFR for short) on the chip related to the control of ADC, which are:

AMUX0SL——AMUX0 channel selection register, the reset value is 00000000;

MAX0CF——AMUX0 configuration register, reset value is 00000000;

ADC0CF——ADC0 configuration register, reset value is 11111000;

ADC0CN——ADC0 control register, reset value is 00000000;

ADC0H——ADC0 data word MSB register, reset value is 00000000;

ADC0L——ADC0 data word LSB register, reset value is 00000000;

ADC0GTH——ADC0 lower limit data high byte register, the reset value is 11111111;

ADC0GTL——ADC0 lower limit data low byte register, the reset value is 11111111;

ADC0LTH——ADC0 upper limit data high byte register, the reset value is 00000000;

ADC0LTL——ADC0 upper limit data low byte register, the reset value is 00000000;

AMX1SL——AMUX1 channel selection register, the reset value is 00000000;

ADC1CN——ADC1 control register, reset value is 00000000;

ADC1CF——ADC1 configuration register, reset value is 11111000;

ADC1——ADC1 data word register, reset value is 00000000;

REF0CN——Reference voltage control register, reset value is 00000000.

ADC is an important function of mixed-signal controllers. If you want to be proficient in application programming, you must have a clear overall understanding of its related factors.

1 ADC Accuracy and Channels

F020 uses TQFP100 package, and there are 8 chip pins (pins 18 to 25) dedicated to analog input, which are the input ends of 8-channel 12-bit ADC. The conversion accuracy of each 12-bit channel is its own ±1LSB (least significant bit). In fact, there is only one 12-bit successive approximation register (SAR) ADC, and there is a multiplexer with 9-channel input (configurable analog multiplexer AMUX) between it and each input end. The 9th channel of AMUX is connected to the temperature sensor. In F020, the 12-bit ADC is called ADC0, and there are 8-channel 8-bit in-system programmable (ISP) ADC circuits called ADC1. Its 8 external pins are multiplexed with P1 port, and the internal structure is similar to ADC0, except that the number of bits converted is 8 bits, and the conversion accuracy is 8 bits ±1LSB.

Each pair of ADC0 ports can be programmed to be single-ended input or differential input respectively. The port pairing for differential input is 0-1, 2-3, 4-5, 6-7, which is determined by the lower 4 bits of the channel selection register AMUX0SL and the lower 4 bits of the channel configuration register AMUX0CF. In AMX0CF, bits 3 to 0 correspond to 2 pin channels respectively. Bit value = 0 indicates an independent single-ended input (the reset value is single-ended input); bit value = 1 indicates a differential input pair. When selecting differential input corresponding to AMX0CF, AMUX0SL is only valid when an even number (including 0) channel is selected (Note: When the lower 4 bits of AMUX0SL are 1xxx, the temperature sensor is selected regardless of the value of the lower 4 bits of AMX0CF).

When bit 3 of REF0CN is set to "1", the temperature sensor is allowed to be used; when it is set to "0", the output of the temperature sensor is high impedance. The value of the temperature sensor can be used to correct the nonlinearity of the parameter or to record and adjust the data related to temperature.

2 ADC speed and startup

The ADC rate in the C8051F series microcontrollers can be programmed, but at least 16 system clocks are required. Generally, a tracking/holding capture time of 3 system clocks (>1.5 μs ) is automatically added before conversion. The method to set the ADC rate in F020 is to configure bits 7 to 3 of the register ADCxCF (x is 0 or 1), and its reset value is 11111 (bits 7 to 3 = SYSCLK/CLK SAR-1).

Generally, the ADC must be in tracking mode before starting. If bit 6 of the control register ADCxCN is "0", it will always be in tracking mode (at this time, starting any of the four start modes can be 3 system clocks faster than starting tracking); if it is "1", there are four tracking start modes to choose from, that is, assign values to bits 3 to 2 in ADCxCN: 00 is tracking when writing 1 to ADBUSY (software command); 01 is timer 3 overflow tracking; 10 is CNVSTR rising edge tracking (external signal); 11 is timer 2 overflow tracking.

When reset, bit 7 of ADCxCN is 0, which means it is in shutdown state. At the end of each conversion, bit 5 of ADCxCN is "1", and the falling edge of bit 4 (busy flag) triggers a structure interrupt. These status bits can also be queried by software.

3 ADC reference and gain

The F020 has a 1.2V, 15×10 -6/℃ bandgap voltage reference generator and a two-times gain output buffer on the chip. The 2.4V reference voltage (VREF) can be connected to ADC0, ADC1 and DAC through external pins. VREF has an external load capacity of 200 μA (it is recommended to connect a load resistor to the ground when driving an external load). When the ADC uses bias, bit 1 in the reference source control register REFcCN must be set to "1"; if it is "0", the internal bias is turned off. At this time, the external reference voltage can be used through the VREF pin (pin 12). The external reference voltage must be less than VAV±0.3V (and greater than 1V). When the ADC or DAC is not used, bit 0 of REFxCN can be set to "0" to put the buffer amplifier in power saving mode (output is high impedance).

When bit 4 of REF0CN is set to "0", ADC0 is biased with VREF, and when it is set to "1", it is biased with DAC0 output; when bit 3 of REF0CN is set to "0", ADC1 is biased with VREF, and when it is set to "1", it is biased with AV+.

In the ADC circuit of F020, there is an internal amplifier (PGA) with programmable gain behind the input multiplexer AMUX. It is particularly useful when the voltage signal ranges of the inputs of the analog channels are very different, or when a signal with a large DC offset needs to be amplified (in differential input mode, the DAC can be used to provide DC offset). The setting method is to configure bits 2 to 0 in ADCxCF (000 corresponds to a PGA gain of 1; 001 corresponds to 2; 010 corresponds to 4; 011 corresponds to 8; 10x corresponds to 16, and 11x corresponds to 0.5). The gain here also works on the temperature sensor signal. When the gain is 1, VTEMP=0.002 86(V/℃)(TEMPC)℃+0.776V.

4 ADC Data and Control

Corresponding to single-ended input, the ADC result data word format is: 0V——0000, VREF——0FFF or FFF0.

Corresponding to differential input, the ADC result data word format is 2's complement: VREF——07FF, 0——0000, -VREF——F800 or 8000.

Setting Bit 0 of ADCxCN to '0' will right-align the result; setting it to '1' will left-align the result. When the input is differential, the extra high bits generated by right alignment are the sign extension bits.

The C8051F series microcontroller also has a data-related window interrupt generator or programmable window detector, also called the ADC upper (lower) limit data register ADC0G (L) TH (L), which monitors a key voltage in the background. When the conversion data is within (or outside) the specified window, the controller is requested to request a conversion end interrupt. When an interrupt is required within the window, the upper limit register LT is loaded with the high window number, and the lower limit register GT is loaded with the low window number; if an interrupt is required outside the window, the lower limit register GT is loaded with the high window number, and the upper limit register LT is loaded with the lower window number.

When reset, the status of the ADC part is: internal voltage reference buffer is off, internal bias is off, internal sensor is off, ADC is disabled, conversion result data register is right-aligned, 12-bit ports are all single-ended inputs, ports point to AIN0, SAR conversion is 33 system clocks, internal amplifier gain is 1, lower limit data register is FFFFH, upper limit data register is 0000H.

In order to correctly apply the ADC function, the following sequence should be followed to program the various elements related to ADC in F020: set reference voltage > set ADC enable > set tracking (start) mode > set data alignment > configure channel > select channel > set conversion clock and gain > set window detection upper and lower limits > start conversion. The sequence of operating SFR (taking 12 bits as an example) is: REF0CH > ADC0CN > AMX0C > AMUX0SL > ADC0CF > ADC0GTH > ADC0GTL > ADC0LTH > ADC0LTL > ADC0CN or other start methods.