Modern power module and device application technology

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Modern power module and device application technology [Copy link]

In the past 20 years, the rapid development of power devices and their packaging technology has led to great changes in the field of power electronics technology. Today's market requires power electronic devices to have a wide range of applications, tailor-made solutions, integration, intelligence, smaller size and weight, more efficient chips, better quality and lower price, longer life and shorter product development cycle. In the past few years, many research and development results have continuously provided new, economical and safe solutions, thus introducing power modules into a series of industrial and consumer fields.

Therefore, it is necessary to conduct a comprehensive series introduction on the application technology of power modules, such as selection, drive, protection, cooling, parallel and series connection, and soft switching circuits.

1 IGBT and MOSFET power modules

1.1 Scope of application

As shown in Figure 1, many current power electronic circuits can be realized by power MOSFET or IGBT. They have appeared on the market since the 1980s. Compared with traditional thyristors, they have a series of advantages, such as the ability to be turned off (including in short-circuit state), no need for a snubber network, simple control unit, short switching time, and low switching loss.

Figure 1 Application scope of power semiconductors

Today, power electronics technology continues to penetrate new application areas, thanks primarily to the rapid development of IGBTs and power MOSFETs. At the same time, their applications are also deepening in their existing fields. A few years ago, high-voltage bipolar power transistors were widely used. Now, they can only be found in a few exceptional cases, and their position has been almost completely replaced by IGBTs.

In applications with currents of tens of A or more, power MOSFETs and IGBTs are mostly insulated power modules containing silicon chips. These modules contain one or more transistor units, diodes (freewheeling diodes) matching the transistors, and in some cases passive components and intelligent parts.

Although the power module has the disadvantage of only being able to be cooled on one side, it is still widely used in high-power power electronics technology, competing with the flat-plate IGBT/diode devices that came out at the same time. Although the flat-plate device can dissipate about 30% more heat loss under the condition of double-sided cooling, the power module is still widely welcomed by users. In addition to the easy installation, the reason also lies in the insulation between the chip and the heat sink of the module, the combinability of multiple different components inside it, and the low cost due to mass production.

In today's market, although various competitive power devices are constantly developing, IGBT modules have won steadily and their power range is constantly extending. Currently produced IGBT modules have forward blocking voltages of 6.5kV, 4.6kV, 3.3kV and 2.5kV. Based on this, MW-class converters with voltages up to 6kV (using circuits with IGBTs in series) have appeared.

On the other hand, MOSFETs are being used in increasingly higher frequency ranges. Today, using appropriate circuit topologies and packaging technology, larger currents can be achieved above 500kHz.

IGBT and MOSFET modules have become basic components of integrated electronic systems, and are also becoming basic components of integrated electromechanical systems.

1.2 Structure and basic functions

The power MOSFET and IGBT described below are both n-channel enhancement type because they represent the mainstream of transistors that make up power modules.

Under the action of a positive driving voltage, a piece of p-conducting silicon material will form a conductive channel. At this time, the conductive carriers are electrons (majority carriers). After the driving voltage disappears, the device is in the cut-off state (self-cut-off).

In most cases, a vertical structure is used as shown in Figures 2 and 4. Here, the gate and source (MOSFET) or emitter (IGBT) are located on the top surface of the chip, while the bottom surface of the chip forms the drain (MOSFET) or collector (IGBT). The load current passes vertically through the chip outside the channel.

The power MOSFET shown in FIG. 2 and the IGBT shown in FIG. 4 have a planar gate structure, that is, in the on state, the conductive channel is lateral (horizontal).

The planar gate (developed into a double diffused gate in modern high-density transistors) is still the dominant gate structure in power MOSFETs and IGBTs.

Planar MOSFET and IGBT structures are transplanted from microelectronics technology. Their drain or collector is composed of n ⁺ (MOSFET) or p ⁺ (IGBT) well regions, located on the chip surface. The load current flows horizontally through the chip. With the help of an oxide layer, the n region can be isolated from the substrate, making it possible to integrate multiple mutually insulated MOSFETs or IGBTs with other structures on a chip.

Since planar transistors have a current density of only 30% of that of vertical structures and require significantly more mounting area, they are mainly used in complex single-chip circuits.

From a structural point of view, power MOSFET (Figure 2) and IGBT (Figure 4) are composed of numerous silicon micro-cells. The number of cells per cm2 chip can reach 8.2×105 ⁽^the latest MOSFET with a withstand voltage of 60V) and 1×105 (high withstand voltage IGBT).

Figure 2 and Figure 4 show that MOSFET and IGBT have similar control region structures.

The n ^{- region forms a space charge region in the off state. The p-conducting well region is implanted in it, with a lower doping concentration (p-}⁾ at the edge and a higher doping concentration (p ⁺ ) in the center.

In these wells there are layers of n ⁺ silicon, which are connected to the metal aluminum surface of the source terminal (MOSFET) or emitter terminal (IGBT). On top of these n ⁺ regions, a thin SiO2 insulating layer is first implanted _, and then the control region (gate) is formed, for example, using n ⁺ polysilicon material.

When a sufficiently high forward drive voltage is applied between the gate and source (MOSFET) or emitter (IGBT), an inversion layer (n-conduction channel) will be formed in the p-region under the gate. Through this channel, electrons can flow from the source or emitter to the n ^- drift region.

MOSFET and IGBT have similar structures up to the n ^- region. They appear in the third region, which determines their different performances.

1.2.1 Power MOSFET

Figure 2 clearly shows the structure and function of an n-channel enhancement mode vertical power MOSFET. The gate structure in Figure 2 is a planar structure.

(a) MOSFET unit and the direction of charge flow when it is turned on (b) General electrical symbol

Figure 2 Power MOSFET (Siemens SIPMOS)

In MOSFET, the above layered structure is realized on an n ⁺ conductive silicon substrate by epitaxial growth, implantation, diffusion, etc. The back side of the silicon substrate forms a drain.

When voltage is applied between the drain and source to generate an electric field, electrons flowing to the drift region are attracted to the drain, which reduces the space charge. At the same time, the drain-source voltage decreases, allowing the main current (drain current) to flow.

Because all the electrons that form the current in the drift region are majority carriers, there will be no flooding of two types of carriers in the high-resistance n ^{- region. Therefore, MOSFET is a unipolar device.}

In low-voltage MOSFET devices, the resistance of the microcell accounts for about 5% to 30% of the on-state resistance of the MOSFET. For high-cutoff voltage MOSFETs, about 95% of its on-state resistance is determined by the resistance of the n ^- epitaxial region.

Therefore, the on-state voltage drop

V _DS(on) = I _DR _DS(on) (1)

Where: ID _is the drain current;

R _DS(on) is the on-state resistance.

R _DS(on) = kV _(BR)DS（2）

Where: k is the material constant. When the chip area is 1 cm ² , k=8.3×10 ^－9 A ^－1 ;

V _(BR)DS is the drain-source forward breakdown voltage.

For MOSFETs currently on the market, when their cut-off voltage is greater than 200-400V, the theoretical limit of their on-state voltage drop is always greater than that of bipolar devices of the same size, while their current carrying capacity is less than the latter.

On the other hand, the charge transport undertaken by the majority carriers alone does not have any storage effect, so it is easy to achieve extremely short switching times. Of course, in devices with large chip sizes (high withstand voltage/high current), the drive current required to charge and discharge the internal capacitor will be quite large, because the capacitance per cm2 ^of chip area is about 0.3μF.

These capacitances, determined by the physical structure of the MOSFET, are its most important parasitic parameters. Figure 3 shows their origin and equivalent circuit diagram. Table 1 explains the origin and symbols of the various parasitic capacitances and resistances in Figure 3.

(a) Parasitic elements within the cell structure

(b) Equivalent circuit with parasitic elements

Figure 3 Power MOSFET unit and its main parasitic elements

Table 1 Parasitic capacitance and resistance of MOSFET

symbol	name	origin
C _GS	Gate-source capacitance	The overlap of the gate and source metallization depends on the gate-source voltage but is independent of the drain-source voltage.
CDS	Drain-source capacitance	The junction capacitance between the n ^{- drift region and the p-well region depends on the cell area, breakdown voltage, and drain-source voltage.}
GD	Gate-drain capacitance	Miller capacitance, resulting from the overlap between the gate and the n ^{- drift region.}
R _G	Gate internal resistance	The resistance of the polysilicon gate is often accompanied by additional series resistance in modules with multiple chips connected in parallel to weaken oscillations between chips.
R _D	Drain resistance	n ^– The resistance of the drift region, which accounts for the majority of the MOSFET’s on-state resistance.
R _W	p-well lateral resistance	The resistance between the base and emitter of a parasitic npn bipolar transistor.

1.2.2 IGBT

Figure 4 clearly shows the structure and function of an n-channel enhancement type vertical IGBT. The IGBT in the figure has a non-punch-through (NPT) structure and a planar gate.

(a) IGBT unit and its charge distribution symbol when it is turned on (b) General electrical

Figure 4 NPT structure IGBT

Unlike MOSFET, there is a p ⁺ conduction region under the n region of IGBT, which leads to the collector.

When the electrons flowing through the n ^- drift region enter the p ⁺ region, they will cause positive charge carriers (holes) to be injected from the p ⁺ region into the n ^- region. These injected holes flow from the drift region to the p-region at the emitter end, and also flow laterally into the emitter through the MOS channel and the n-well region. Therefore, in the n-drift region, there is an excess of carriers that constitute the main current (collector current). This carrier enhancement effect leads to a reduction in the space charge region and a reduction in the collector-emitter voltage.

Although IGBT needs to add the turn-on voltage of the collector end pn junction compared with the pure resistance conduction characteristics of MOSFET, for IGBT devices with high cut-off voltage (starting from about 400V), because of the minority carrier enhancement effect in the high-resistance n ^- region, the conduction voltage drop of the device is still lower than that of MOSFET. In this way, on the same chip area, IGBT can be designed with a larger current than MOSFET.

On the other hand, during the turn-off period and the subsequent rise of the collector voltage, most of the p-storage charge Qs that has not yet been released must be recombined in the n-region. Qs increases almost linearly ^when_{the load}_current is small, and is determined by the following exponential relationship in the rated current and overcurrent region:

Q _s～I ^0.8～1When the current is less than the rated current;

Q _s～I ^0.5When the current is equal to or greater than the rated current;

Qs～V ( _BR_)CE^2～2.7 .

The build-up and dissipation of the stored charge induces switching losses, delay time (storage time), and collector tail current at turn-off.

At present, in addition to the non-punch-through structure shown in Figure 4, the punch-through structure (PT=Punch Through) IGBT has also been used. The original IGBT was formed based on the latter.

The basic difference between the two structures is that there is a high diffusion concentration n ^{+ layer (buffer layer) between the}^n- and p ⁺ regions of the PT-type IGBT . In addition, the manufacturing processes of the two are also different.

In PT-type IGBT, n ⁺ and n- ^layers are usually grown epitaxially on a p-type substrate. The basic material of NPT-type IGBT is a weakly diffused n-type thin silicon wafer, on the back of which a p ⁺ region at the collector end is implanted. The top structure of the two IGBTs is the same, both of which are planar MOS control regions.

Figure 5 compares the two IGBT structures and the electric field intensity distribution in the forward cut-off state.

(a) PT type IGBT

(b) NPT type IGBT

Figure 5 IGBT structure and electric field intensity distribution in the forward cutoff state

For a PT-type IGBT or IGET (E: epitaxial structure), in the forward cutoff state, the space charge region covers the entire n ^- region. In order to make the growth layer as thin as possible even at high cutoff voltage, the electric field strength at the end of the n ^- drift region needs to be weakened by a high diffusion concentration n ⁺ buffer layer.

On the contrary, for NPT type IGBT or IGHT (H: Homogenous structure), its n ^- drift region has enough thickness to absorb the field strength of the maximum cut-off voltage in the forward cut-off state. Therefore, within the allowable operating range, the phenomenon of the electric field extending outside the entire n ^- region (punch-through) does not occur.

In order to further describe the function of IGBT and the different characteristics of PT and NPT type devices, it is necessary to observe the equivalent circuit derived from the IGBT structure [Figure 6 (b)]. Similar to Figure 3, the origin and symbols of the parasitic capacitance and resistance shown in Figure 6 can be obtained, as listed in Table 2.

(a) Parasitic elements within the cell structure

(b) Equivalent circuit with parasitic elements

Figure 6 IGBT (NPT structure) unit and its main parasitic components

Table 2 IGBT parasitic capacitance and resistance

symbol	name	origin
C _{G E}	Gate-emitter capacitance	The overlap of the gate and emitter metallization depends on the gate-emitter voltage but is independent of the collector-emitter voltage.
CCE	Collector-emitter capacitance	The junction capacitance between the n ^{- drift region and the p-well region depends on the surface area of the cell, the drain-source breakdown voltage, and the drain-source voltage.}
G _GC	Gate-Collector Capacitance	Miller capacitance, resulting from the overlap between the gate and the n ^{- drift region.}
R _G	Gate internal resistance	The resistance of the polysilicon gate is often accompanied by additional series resistance in modules with multiple chips connected in parallel to weaken oscillations between chips.
R _D	Drift region resistance	n ^– Resistance of the drift region (base resistance of a pnp transistor).
R _W	p-well lateral resistance	The resistance between the base and emitter of a parasitic npn bipolar transistor.

Leaving aside the capacitance and resistance inside the device, the equivalent circuit of the IGBT contains the ideal MOSFET that also exists in the MOSFET structure, and a parasitic npn transistor, namely n ⁺ emitter region (emitter) / p ⁺ well region (base) / n drift region (collector). In this parasitic structure, the resistance of the p ⁺ well region located below the emitter is regarded as the base-emitter resistance R _W. In addition, the following region combination constitutes a pnp transistor, namely p ⁺ collector region (emitter) / n ^- drift region (base) / p ⁺ well region (collector). This pnp transistor together with the above npn transistor constitutes a thyristor structure.

This parasitic thyristor latch-up effect can occur in the on-state (provided that a certain critical current density is exceeded, which decreases with increasing chip temperature) or in the off-state (dynamic latch-up, caused by a higher hole current than in the on-state operation). The latter occurs when equation (3) is satisfied.

M ( α _npn + α _npn ) = 1 (3)

Where: M is the multiplication coefficient;

α _pnp , α _npn =α _T γ _E , is the common base current gain of a single transistor,

α _T is the base transmission coefficient;

γ _E is the emitter efficiency.

The occurrence of lock-up can cause the IGBT to lose control and even be damaged.

For modern IGBTs, the following design measures can effectively prevent the occurrence of latching effects under all permissible static and dynamic operating conditions. For example, with proper design, the current density required for dynamic latching during shutdown can be as much as 15 times the rated current.

For this purpose, the base-emitter resistance of the transistor can be reduced to such a small value by the following measures that the turn-on voltage of the base-emitter diode of the npn transistor cannot be reached in any permissible operating state. These measures are:

1) Enhance the diffusion concentration of the p ⁺ well region directly under the n emitter ;

2) Shorten the size of the n-emitter.

In addition, by adjusting the current gain of the pnp transistor, its hole current (the base current of the npn transistor) is maintained as small as possible. Of course, it is necessary to take into account the switching characteristics, impact resistance, and on-state characteristics to achieve a good compromise. The latter is also determined to some extent by the design of the pnp transistor.

This compromise is implemented differently in PT and NPT IGBTs.

In PT-type IGBT, the hole injection efficiency (emitter efficiency) from the p ⁺ region to the n ^{- drift region is very high because its substrate is relatively thick. Its pnp current amplification factor can only be reduced by adjusting the base transmission coefficient (n}^- drift region, n ⁺ buffer region). For this reason, the carrier lifetime in the n-region can be reduced by additional recombination centers (for example, using gold element diffusion or electron radiation technology). Its hole current accounts for about 40% to 45% of the total current.

NPT-type IGBT is different from it. Its p-emitter region at the collector end is formed by implantation and is significantly thinner than the substrate of PT-type IGBT. Therefore, when producing silicon wafers, the distribution of diffusion concentration on the material can be easily and accurately adjusted. This extremely thin p ⁺ layer ensures that the emitter efficiency of the pnp transistor is low (γ _E = 0.5), so that it is no longer necessary to reduce the base transmission coefficient by reducing the carrier lifetime. Its hole current accounts for about 20% to 25% of the total current.

Compared with PT-type IGBT, NPT-type IGBT has lower emitter efficiency, longer carrier lifetime, and parameters can be controlled more accurately. Its advantages are as follows:

1) The forward conduction voltage has a positive temperature coefficient (automatically statically equalizes current when connected in parallel);

2) The tail current at turn-off is small, but in some cases the time is long, the turn-off loss is low at T _j = 125 ° C, the switching time is short (at hard turn-off) and the switching loss is low;

3) The temperature dependence of the switching time and switching losses (at T _{j = 125 °C) as well as the tail current is significantly lower;}

4) It has a better current limiting effect when overloaded, so it has a higher overload capacity.

Compared with the epitaxial growth substrate used in PT-type IGBTs, the homogeneous n ^- substrate currently used as the basic material for NPT-type IGBTs is easier to produce, provided that it has the ability to handle extremely thin silicon wafers.

1.3 Static characteristics

The output characteristics of MOSFET and IGBT modules are shown in Figure 7. The first quadrant shows that the module can withstand high cut-off voltages and shut off large currents. A more precise definition for the blocking characteristics of the first quadrant would be "blocking state" (similar to the definition in thyristors), but this concept is rarely used in transistors. In the following, we will use the name forward cut-off state or (where there is no confusion) cut-off state.

Figure 7 Basic output characteristics of power modules

_{Through the action of the control electrode, the power MOSFET and IGBT can be switched from the forward cut-off state (operating point OP 1} in Figure 7 ) to the on state (OP ₂ ). In the on state, the device can pass the load current. The active region (amplification region) between the two states is crossed during the switching process.

Unlike an ideal switch, the forward cutoff voltage and on-state current of the device are both finite. In the forward cutoff state, there is a residual leakage current (forward cutoff current), which will cause cutoff losses in the transistor. In the on-state, there is a residual voltage drop between the main circuit terminals that depends on the on-state current, which is called the on-state voltage drop, which will cause on-state losses. The maximum on-state loss in the static on-state (not during the switching process) is given by the hyperbola representing the on-state loss in the output characteristics.

The third quadrant shows the reverse characteristics of the module, under the condition that a reverse voltage is applied between the main circuit terminals. The characteristics of this area are determined by the performance of the transistor itself (reverse cutoff type, reverse conduction type) and the characteristics of the diode in the power module (in series or reverse parallel with the transistor).

1.3.1 Power MOSFET

Based on the above principle, the output characteristics of the power MOSFET can be derived as shown in Figure 8 (a).

(a) Output characteristics of power MOSFET (n-channel enhancement type)

(b) Transfer _{characteristics}ID = f ( V _GS )

Figure 8 Power MOSFET output characteristics and transfer characteristics

1.3.1.1 Forward cutoff state

When a positive drain-source voltage V _DS is applied , if the gate-source voltage V _GS is less than the gate-source turn-on voltage V _GS(th) , only a small leakage current I _DSS flows between the drain and the source. When V _DS increases, I _DSS also increases slightly. When V _DS exceeds a certain maximum allowable value V _DSS , the pin junction (p ⁺ well region/n ^- drift region/n ⁺ epitaxial growth layer) will undergo a lock-up phenomenon (lock-up voltage V _(BR)DSS ). This lock-up voltage physically corresponds roughly to the breakdown voltage V _CER of the parasitic npn bipolar transistor in the MOSFET structure . The npn transistor is composed of n source region (emitter) - p ⁺ well region (base) - n ^- drift region/n ⁺ epitaxial growth layer (collector), as shown in Figure 3.

The current amplification effect caused by the lock-up phenomenon of the collector-base diode may cause the parasitic bipolar transistor to turn on, resulting in the destruction of the MOSFET.

Fortunately, the base and emitter regions are almost short-circuited by the source metallization structure, and only the lateral resistance of the p+ well region exists between the two regions.

By applying various design measures, such as fine MOSFET cells, uniform cell layout, low-resistance p ⁺ well area, optimized edge structure and strictly unified process, advanced MOSFETs can achieve very small cell lock-in current. In this way, the conduction phenomenon of the parasitic bipolar transistor structure can be basically prevented under strict compliance with given parameters. Therefore, for this type of MOSFET chip, an allowable lock-in energy EA can be defined for single pulses and periodic loads (the lock-in energy is limited by the maximum allowable chip temperature).

In the case where a power module is formed by connecting multiple MOSFET chips in parallel, it is impossible to achieve absolute balance between the chips, so only the maximum EA value that can be guaranteed by a single chip is allowed.

1.3.1.2 On state

When both the drain-source voltage V _{DS and}_the drain current ID are positive, the forward conduction state can be divided into two regions, as shown in the first quadrant in Figure 8(a).

1) Active region When the gate-source voltage is only slightly greater than the gate turn-on voltage, the saturation effect of the current in the channel will produce a considerable voltage drop (the horizontal line of the output characteristic). At this time, _ID_iscontrolled by VGS .

In Figure 8(b), the transfer characteristics can be described by means of the positive transfer _slopegfs .

g _fs =d I _D /d V _GS = I _D /( V _GS - V _GS(th) ) (4)

In the active region, the forward transfer slope increases with increasing ID and source voltage, and decreases with increasing _{chip temperature.}

Because the power module composed of multiple MOSFET chips connected in parallel is only allowed to work in the switching state, the active area is only passed through during the turn-on and turn-off processes.

Generally speaking, manufacturers do not allow such modules to operate stably in the active region. The reason is that V _GS(th) decreases with increasing temperature, so small manufacturing deviations between individual chips can cause an unbalanced temperature rise.

2) Resistive region In the switch working state, if _{ID is determined only by the external circuit, it is in the resistive region called the on-state. The conduction characteristics at this time can be described by the on-state resistance, that is, the quotient of the drain-source voltage VDS}and the _draincurrent ID _.In the large signal region, the on-state voltage follows the relationship of formula (5).

V _DS(on) = R _DS(on)I _D (5)

R _DS(on) depends on the gate-source voltage V _GS and the chip temperature. In the normal operating temperature range of MOSFET, it will approximately double from 25℃ to 125℃.

1.3.1.3 Reverse operation

When operating in the reverse direction (third quadrant), if V _GS is less than V _{GS (th)} , the MOSFET will show a diode characteristic as shown by the solid line in Figure 8 (a). This characteristic is caused by the parasitic diode in the MOSFET structure. The conduction voltage of the collector-base pn junction or the source-drain pn junction (bipolar current of the reverse diode) determines the conduction characteristics of the MOSFET in the reverse direction as shown in Figure 9 (a).

This bipolar reverse diode can be operated up to the current limit given by the MOSFET.

However, in practical applications, this reverse diode will result in:

1) Large conduction losses, which, together with the losses of the MOSFET itself, must be dissipated;

2) When MOSFET is used as a hard switch, it has poor turn-off characteristics, which limits the application range of MOSFET.

As shown in Figure 9(b), in principle, as long as the gate-source voltage is greater than the gate turn-on voltage, the channel of the MOSFET can be controlled to the on state even if the drain-source voltage is negative.

If the gate-source voltage is kept below the turn-on voltage of the reverse diode (for example, by connecting a Schottky diode in parallel), the reverse current between the drain and source is only a unipolar electron current (majority current). In this way, its turn-off characteristics are the same as those of MOSFET.

The reverse current depends on VDS and VGS, as shown by the dashed line in Figure 8(a).

In Figure 9 (c), when the channel is on and there is a conducting bipolar reverse diode (drain-source voltage is greater than gate turn-on voltage), a current operation condition combining the two will occur. Compared with a MOSFET with a simple parallel diode, the injected carriers can also diffuse laterally, thereby increasing the conductivity of the MOSFET, which ultimately leads to a decrease in the on-state voltage.

(a) When the channel is closed (bipolar current)

(b) When the channel is controlled to turn on and VDS is a small negative value (unipolar current)

(c) When the channel is controlled to turn on and V _DS is a large negative value (mixed current)

Figure 9 Reverse operation of power MOSFET

1.3.2 IGBT

According to the working principle of the IGBT described above, the output characteristics shown in FIG10 can be obtained.

(a) Output characteristics of IGBT (n-channel enhancement type)

(b) Transfer characteristics I _C = f ( V _CE )

Figure 10 Output characteristics and transfer characteristics of IGBT

1.3.2.1 Forward cutoff state

_{Similar to the principle of MOSFET, when the collector-emitter voltage VCE is positive and the} gate-emitter voltage VGE is less than the gate-emitter turn-on voltage _{VGE(th), there is only a small collector-emitter leakage current ICES between the collector and emitter terminals of the IGBT. ICES}increases _slightly with the _{increase of VCE}_. When VCE is greater than a _certain , maximum allowable collector-emitter voltage VCES _{, the pin junction (p+ well region/n-drift region/n+ epitaxial growth layer) of the IGBT will experience a}_locking effect. From a physical point of view, VCES corresponds to the breakdown voltage VCER of the pnp bipolar transistor in the IGBT structure.

When the lock-in phenomenon occurs, the current amplification effect caused by the collector-base diode may cause the bipolar transistor to turn on, thereby causing damage to the IGBT.

Fortunately, the base and emitter regions are almost short-circuited by the metallized emitter. They are separated only by the lateral resistance of the p+ well region.

By applying various design measures, similar to those taken for MOSFET, the cell lock-in current of the IGBT can be maintained at a very low level, so that the forward cut-off voltage can be highly stable.

1.3.2.2 On state

When the collector-emitter voltage and collector current are both positive, the IGBT is in the forward conduction state and can be further divided into two regions.

1) Active region When the gate-emitter voltage V _GE is only slightly greater than the turn-on voltage V _GE(th) , a considerable voltage drop (horizontal line in the output characteristic) will appear in the channel due to the saturation effect of the channel current. At this time, the collector current changes with V _{GE .}

Similar to MOSFET, the transfer characteristics shown in Figure 10(b) are described by _the forward transfer slope gfs .

g _fs =d I _C /d V _GE = I _C /( V _GE - V _GE(th) ) (6)

The conversion slope of the transfer characteristic in the linear amplification region increases with the increase of collector current _ICand collector- _emitter voltage VCE , and decreases with the decrease of chip temperature.

In a power module consisting of multiple IGBT chips connected in parallel, this area is only passed through during the switching process.

Generally speaking, steady-state operation of the module in this region is not allowed (just like MOSFET modules). The reason is that V _GE(th) decreases with increasing temperature, so small manufacturing deviations between individual chips may cause temperature rise imbalance.

2) Saturation region During the switching process, once the I _C is determined only by the external circuit, it is in the so-called saturation region, also known as the on-state (the steep slope in the output characteristic). The main parameter of the on-characteristic is the residual voltage V _CEsat (collector-emitter saturation voltage drop) of the IGBT. At least for IGBT devices with high cut-off voltage, due to the minority carrier flooding in the n-drift region, the saturation voltage drop of the IGBT is significantly lower than the on-state voltage drop of the same type of MOSFET.

As mentioned before, the V _CEsat of PT-type IGBT decreases with increasing temperature in the rated current region, while for NPT-type IGBT, it increases with increasing temperature.

1.3.2.3 Reverse characteristics

In the reverse operation state, as shown in the third quadrant in Figure 10, the pn junction at the collector end of the IGBT is in the cut-off state. Therefore, unlike the MOSFET, the IGBT does not have the ability to conduct in the reverse direction.

Although there is a high-resistance pin diode in the IGBT structure, the reverse cutoff voltage of the current IGBT is only around tens of V, especially for NPT-type IGBTs. The reason is that when designing the chip and its edge structure, people focus on pursuing high forward cutoff voltage and optimizing the heat dissipation of the collector port.

For some special applications that require IGBT switches to withstand reverse voltage, a hybrid structure has been used so far, that is, a fast diode is connected in series in the module.

Therefore, when the IGBT module is working in static reverse mode, its conduction characteristics are only determined by the characteristics of the external or mixed diode.