Switch-mode GaAs power amplifiers shine in WLAN designs

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Switch-mode GaAs power amplifiers shine in WLAN designs [Copy link]

Recent advances in high-speed/high-frequency mixed-signal semiconductor process technology have enabled the advent of fully integrated wireless LAN (WLAN) transmitters, especially those using compute-generated modulation techniques. The combination of fully integrated transmitters and compute-generated modulation techniques has in turn enabled the use of high-efficiency switch-mode power amplifiers in advanced modulation schemes, which were previously considered inappropriate. This development has created a niche for the "Linear Amplification with Nonlinear Devices (LINC)" power amplifier architecture, which can achieve the highest efficiency, output power, and performance in high-data-rate WLAN applications.

LINC-based power amplifier architectures combine switch-mode power amplifiers with the use of additional computational engines to amplify signals with phase and amplitude modulation, such as quadrature amplitude modulation (QAM) and multi-carrier orthogonal frequency division multiplexing (OFDM). Multi-carrier modulation schemes such as OFDM place stringent linearity requirements on the analog RF section of the transceiver. This stringent linearity requirement is even more demanding for the power amplifier in the transceiver due to the corresponding high output power level requirements. The advent of mixed-signal ICs has made it possible to use integrated linearization techniques for power amplifiers based on additional computational engines.

Figure 2: Voltage and current waveforms of a Class D amplifier.

In contrast to the integration of RF and computational circuits in a single CMOS (or Bi-CMOS) chip, external gallium arsenide (GaAs) based PAs offer some significant advantages. This article will explore the benefits of standalone GaAs PAs over integrated silicon solutions, followed by the introduction of three classes of GaAs switch-mode amplifiers that can be used with advanced modulation schemes such as multi-carrier modulation with appropriate LINC computational circuits in the PA’s companion CMOS (or Bi-CMOS) transceiver chip. Performance simulations of a Class F switch-mode PA operating at 5 GHz are also provided.

Advantages of GaAs power amplifier

Although silicon CMOS PAs appear attractive for fully integrated transmitters, external GaAs PAs offer several significant advantages in addition to substrate isolation.

The biggest advantage of GaAs amplifiers is their higher carrier mobility, which allows higher f _t and f _max than silicon , and allows the use of larger devices with higher breakdown voltages at any given frequency. This in turn allows the use of higher bias voltages and correspondingly lower currents at any given output power. Low currents reduce source and drain parasitic capacitances, which limit high operating frequencies and pose a major problem for switch-mode amplifiers.

Figure 3: Class E amplifier voltage configuration.

The transconductance gm of GaAs _is also much higher than that of silicon CMOS. The higher the transconductance, the greater the gain per amplifier stage. This allows fewer stages to be used for any given gain requirement, reducing die area and overall system cost.

Input impedance matching of GaAs pHEMT devices is much easier than that of silicon CMOS devices, thus reducing unwanted mismatch power losses, reducing the die area required for passive matching circuits, and further reducing overall cost.

The metal layers (gold) used in the GaAs process have lower impedance than the metal layers (aluminum and copper) used in silicon CMOS. Therefore, the spiral inductors and MIM capacitors in the passive matching circuit can provide higher Qs and lower losses. The GaAs semi-insulating substrate is also a reason for the higher Qs and lower losses of such inductors and MIM capacitors compared to silicon.

Finally, the semi-insulating substrate reduces the source and drain parasitic capacitance of transistors, making GaAs devices more efficient than silicon CMOS at a given frequency.

Figure 4: Voltage and current waveforms of a Class E amplifier.

Combining the above advantages, it can be clearly seen that GaAs technology has great advantages in the application of microwave power amplifiers. In addition to independent linear amplifiers, GaAs also shows strong advantages in the application of switch-mode power amplifiers. Due to the use of appropriate LINC computing engines in the matching CMOS (or BiCMOS) transceiver chips, these switch-mode power amplifiers are attractive for advanced modulation schemes in high-speed data rate applications.

Switch Mode Power Amplifier

In WLAN design, there are six classes of GaAs power amplifiers: Class A, Class B, Class A/B, Class D, Class E, and Class F. Switch-mode Class D, E, and F amplifiers have higher efficiency than their linear Class A, B, or Class A/B counterparts, but the output impedance is very low or time-varying. In this case, high efficiency can be achieved by limiting (or not allowing) current to pass through the active device if there is a voltage drop across the output terminals. If current flows through the device, efficiency can be improved by limiting (or not allowing) the voltage at its output terminals.

Let’s take a closer look at Class D, E, and F amplifiers. Figure 1 shows a transformer-coupled voltage-switching configuration for a Class D amplifier, with voltage and current waveforms shown in Figure 2.

In Figures 1 and 2, the input signal Vin and its complement cause the two transistors to turn on and off alternately. During the half cycle when the lower transistor is in the "on" state, its drain voltage is zero. At this time, the voltage Vcc is generated in the lower half of the transformer primary coil, which is converted to a voltage (n/m) Vcc on the secondary coil according to the turns ratio (n/m). Therefore, the drain voltage of the upper transistor is +2Vcc.

Figure 5: Class F amplifier voltage configuration.

During the half cycle when the upper transistor is in the "on" state, the voltage Vcc is generated in the upper half of the transformer primary winding, which is transformed into -(n/m)Vcc on the secondary winding according to the turns ratio. Therefore, the drain voltage of the lower transistor is +2Vcc.

The secondary voltage is a square wave, and its fundamental frequency passes through the output resonator to produce a sinusoidal output current. On the output coil, the two "half-sine waves" flow alternately in their upper and lower halves (thus flowing alternately through the upper and lower transistors), so the output coil supports the sinusoidal output current. Since current flows through each device when the drain voltage is zero, and no current flows when the drain voltage is +2Vcc, these devices do not absorb power, and their efficiency can theoretically reach 100%.

Although Class D amplifiers have a theoretical efficiency of 100%, their practical applications are limited by the drain (or collector) parasitic capacitance. This parasitic characteristic prevents the voltage waveform from switching on and off in a timely manner, causing the current flowing through the transistor to generate a voltage at the transistor output.

A similar effect occurs if the load contains large reactive devices. In this case, the drain voltage waveform is still a square wave, but the output current is phase-shifted. Therefore, when turned on, negative current flows through each device, which charges the parasitic capacitance and generates voltage spikes.

The parasitic capacitance problem of Class D amplifiers is solved in the Class E amplifier architecture.

Figure 6: Voltage and current waveforms of a Class F amplifier.

FIG3 shows a single-ended class E amplifier, and its voltage and current waveforms are shown in FIG4 .

Here, a series tuned LoC0 circuit connects the drain to the load, and a bypass capacitor C is connected to ground. The bypass capacitor is composed of the transistor parasitic capacitance and another capacitor (the function of this capacitor is to ensure that no current flows in the transistor when the voltage is present on the drain). This ideal state is achieved by making the drain voltage constantly changing, rather than being limited to a square wave as in a Class D amplifier. It should be noted that this will produce a significant drain voltage overshoot, which must be kept below the breakdown voltage of the device.

To achieve optimal performance, not only must the drain voltage be zero when the device turns on (and begins to generate current), but the slope of the drain voltage must also be zero. This ensures that the current drawn from the bypass capacitor is zero, which in turn ensures that the drain current is zero when the transistor is on. Since the drain-source voltage and drain current are both zero during the transition, the power dissipation of the device is negligible.

Although Class E amplifiers are theoretically 100% efficient, their efficiency is limited by the high Q required to suppress harmonics, which drives the drain voltage down to 0V with a zero slope over time. For Class D amplifiers, changes in load reactance can produce negative drain voltages and/or drain currents during parts of the RF cycle.

The Class F architecture avoids these problems, as well as some of the issues that occur with Class D. Figure 5 shows a single-ended Class F amplifier, and its voltage and current waveforms are shown in Figure 6.

The load network of a Class F amplifier resonates at one or more harmonics as well as the fundamental. The transistor in Figure 5 is a current source that produces a half-sine wave. The fundamental-tuned circuit in the output shunts all harmonics to ground, producing a sinusoidal output voltage. However, the third harmonic resonator has a high impedance (at the third harmonic), which causes the drain voltage of the device to maintain the third harmonic component. The correct amplitude and phase of the third harmonic relative to the fundamental frequency reduces the drain voltage, resulting in higher efficiency.

Figure 7: Simulation of a 0.5 micron GaAs MESFET device operating in class F mode at 5 GHz .

This article uses Agilent's Advanced Design System EDA tool to simulate a 0.5-micron GaAs MESFET operating at 5 GHz in Class F (Figure 7). The drain bias is 5 V and the gate bias is 12 V.

As can be seen from the figure, when the input gate drive voltage V _gate rises from a peak of 1.8V to 2.7V, V _drain gradually changes to a square wave. This is because the amplitude and phase of the third harmonic component gradually change to the correct values required for Class F operation. Once passing through the resonator section of the Class F amplifier, the square wave drain voltage will be converted into a sinusoidal output voltage V _out .

The table of Figure 7 also lists the simulated efficiency and output power of the Class F amplifier when operating in Class F. The simulated efficiency is 86.919%, which is fully consistent with the expected theoretical value for Class F operation.

Power Amplifier Linearization Technology

Like linear power amplifiers, switch-mode power amplifiers used in LINC-based architectures also have linearization requirements to provide high performance for advanced modulation schemes such as OFDM. Linearization compensates for AM-to-AM distortion (compression) and AM-to-PM distortion, thereby providing a clean output signal with very low out-of-band emissions and in-band error vector magnitude (EVM).

Figure 8: Feedback with frequency translation.

Several traditional techniques can be used to overcome linearity issues in transmitters, such as feedback, feedforward, and predistortion. As described below, each technique has its own advantages and limitations. The correct choice of power amplifier linearization technique depends on whether it can relatively easily cope with these different limitations.

Using feedback in RF power amplifiers is not easy. For very nonlinear power amplifiers, very high loop gain must be achieved to achieve the required linearity. Loop instability is caused by various resonances of parasitic coupling, package parasitics, and transient currents, so feedback power amplifiers may be affected by spontaneous oscillations.

However, feedback techniques can be successfully used in a combined upconverter/power amplifier where the high loop gain problem is mitigated by distributing most of the loop gain to lower IF frequencies (which are less likely to resonate).

Figure 8 shows a scenario where the loop gain is allocated to the lower IF frequency. As can be seen from the figure, a portion of the output power is down-converted to the original IF frequency. As a result, the loop will try to make the VRF modulation equal to the VIF modulation.

To ensure stability, the closed-loop phase is not allowed to reach 180 degrees for any frequency where the loop gain is greater than 1. To achieve this, the phase θ of the reference frequency LO (used to downconvert the RF) is set to ensure that it has a safety margin. A significant problem is that the value of θ depends on temperature, process parameters, and output power, making it difficult to ensure stability.

Figure 9: Feed-forward power amplifier architecture diagram.

Feedback techniques for transceivers combined with independent quadrature signal upconversion have been attempted for conventional power amplifiers. Here, quadrature downconversion in the feedback loop reconverts the RF into two quadrature IF components ready for comparison with the original two quadrature IF signals. This architecture has not been widely adopted due to increased complexity and sensitivity to temperature and process.

The output voltage waveform of a nonlinear amplifier can be viewed as an amplified replica of the input signal combined with an error signal. The feedforward architecture can determine this error and remove it from the amplified output waveform (Figure 9).

As can be seen in Figure 9, a portion of the PA output signal is attenuated by a factor equal to the PA gain. The attenuated output signal is compared to the original input signal to produce an error signal. Finally, the error signal is amplified by the same gain of the PA and removed from its output signal. At high frequencies, such as 5 GHz, both amplifiers in the feedforward architecture have significant phase shifts. This phase shift must be compensated using two real-time delay units.

Unlike feedback architectures, feedforward techniques are inherently stable, even with significant phase shifts in each component. However, passive real-time delay elements are lossy, and the achievable linearity depends on the gain and phase (real-time delay) matching of the signals at each subtractor.

Assuming a gain mismatch of 5% and a phase mismatch of 5 degrees, the power suppression of the intermodulation product will be limited to 20 dB. Finally, in order not to affect the total output power, the output subtractor must have low power consumption.

The predistortion architecture provides the inverse input/output (I/O) function of a saturated power amplifier. The predistortion circuit provides increased gain for large amplitude signals before being applied to the power amplifier. In addition, the predistortion circuit provides an inverse phase change to compensate for any amplitude-dependent insertion phase.

The predistortion circuit can be operated at the RF frequency of the power amplifier, or at the IF or baseband frequency before upconversion, as shown in Figure 10. If the predistortion circuit is used before upconversion, it can be implemented in either analog or digital form.

Figure 10: Predistortion power amplifier architecture diagram.

Since predistortion does not employ any closed feedback loop, there are no stability issues. However, obtaining an accurate inverse input-output function of the PA requires considerable system-level and digital and RF IC design expertise.

Conclusion

Standalone GaAs power amplifiers have many significant advantages over their integrated CMOS (or Bi-CMOS) counterparts. The computational engine in the accompanying receiver chip enables the use of various types of power amplifiers, such as switch-mode architectures, even though such amplifiers are not generally considered for advanced modulation schemes. In addition, the computational engine in the accompanying receiver chip can also apply linearization techniques to the power amplifier.

Although all three classes of switch-mode amplifiers, D, E, and F, are theoretically extremely efficient, the application of class D is limited by its drain (collector) parasitics, and the application of class E is limited by its high Q requirements and sensitivity to load changes. Class F can provide satisfactory performance, including extremely high efficiency, if applied to the appropriate transceiver architecture and implemented using a suitable process.

For wireless designs that use advanced modulation schemes with large peak-to-average ratios, power amplifier linearization is critical to achieving high efficiency and low power consumption. The three commonly used linearization techniques (feedback, feedforward, and predistortion) each have their own unique operating requirements and limitations.

Author: Jim Wight
Chief Architect
Email: jwight@icefyre.com
IceFyre Semiconductor

xujian2000

All the charts are gone. Could you provide the *.pdf file? Thanks!