As mobile phones and other portable electronic devices become more advanced, the power consumption of the system in the working and standby states is also increasing. Therefore, the power management design of portable devices faces new challenges in core voltage, energy management and battery life. Hardware designers have begun to adopt advanced, highly integrated power management devices that feature core voltage scaling and various regulators to provide power to other rails such as memory, I/O, etc. However, these complex solutions do not necessarily provide enough flexibility for system designers. This article will outline an innovative approach to solving the dynamic voltage management problem based on TI's first generation of high-frequency buck converters. System Overview Most modern processors targeting portable applications have an integrated I 2 C interface to connect to an external power management unit. Figure 1 shows an alternative solution for generating an adaptive core supply. The power consumed by the processor core is proportional to the operating frequency and V CORE 2 . The two-chip solution based on the TPS62300 (3MHz synchronous buck converter) and the DAC6571 (10-bit digital-to-analog converter) combines high accuracy with ultra-small voltage steps. Depending on the operating frequency of the processor, the core voltage can be dynamically adjusted to a lower limit very accurately, thereby minimizing power consumption. Using this principle not only reduces power consumption in active mode, but also extends standby time by reducing leakage current in deep sleep mode.  TPS62300: The center of the core voltage Texas Instruments (TI) recently released the TPS62300, which is the flagship product of the new generation of high-frequency buck converters, operating at a switching frequency of 3MHz. The advanced summing comparator voltage mode control topology has promoted a new level of voltage regulation performance. The best transient response and output voltage accuracy can meet the most stringent voltage specifications required by modern cores. The TPS62300 operates with inductors as low as 1.0mH and output capacitors as low as 4.7mF, allowing the use of tiny, low-cost chip inductors. The device is also available in a small chip-scale package (2mm x 1mm x 0.65mm), meeting the needs of mobile phone manufacturers when small form factor solution size is critical. TPS62300: Convenient dynamic voltage scaling Figure 2 shows a simplified TPS62300 block diagram. Its purpose is to illustrate the gain architecture and control loop design of the device. One thing we notice that is different from a traditional regulator is how the output voltage is set. Traditionally, a reference voltage is applied to the positive terminal of the fault amplifier, and the desired output voltage is programmed by sensing the output voltage and dividing it by the reference voltage through an external resistor. The TPS62300 generates an output voltage by amplifying the reference voltage (V REF = 400mV) to two-thirds of the desired output voltage through an internal low-power, low-offset operational amplifier and external resistor programming . This voltage becomes the reference for the "power train" with a DC closed loop gain (A PT ) of 1.5. The fixed closed loop gain in the PA not only provides a constant "small signal" transient response (regardless of the programmed output voltage), but also achieves very tight regulation error ratios and robustness in terms of the L/C combination.  The implementation of the op amp used to amplify the bandgap reference voltage is detailed in Figure 3. This low-offset op amp can be considered an ideal amplifier with a Class A output stage, which is characterized by its ability to source current but not sink current. To realize a linear system with negative feedback, the bandgap buffer amplifier needs to be operated with a DAC voltage lower than V REF (400mV). Only then can current flow out of the ADJ pin and through the R1 and R2 resistors to GND. Assuming the DAC voltage is higher than V REF , V REF allows another loop of current through R 1 and R 2 into the ADJ pin. Since the op amp output stage (MOS1) can only source current, it can no longer operate in linear mode. In this case, the MOS1 transistor impedance used in the voltage follower configuration is high. In fact, to "ride over" the ADJ voltage, we only need to keep the FB voltage higher than the internal reference voltage (V REF ).  If the DAC voltage is higher than ADJ, referenced to the resistance going into the ADJ pin, external default voltage setting resistors R1 and R2 ( 1MW ±30%) should be considered. In effect, R1 and R2 in series form a voltage divider with the resistor going into the ADJ pin. To achieve a DC accuracy of less than 1% over temperature, line, and load variations, we recommend that the resistance value of R1 + R2 be chosen in the 20kΩ range. Table 1 summarizes the operation of the power converter: 
Note 1: Internal reference voltage VREF typical value = 400mV
Note 2: DC power train amplifier APT typical value = 1.5Figure 4 shows the TPS62300 output voltage response vs. DAC voltage. To achieve optimal performance in dynamic voltage management applications, we recommend operating with a DAC voltage above 450mV.  I2C - controlled adaptive voltage scaling: How it works Figure 5 shows the circuit implementation based on TPS62300 and DAC6571. TPS62300 can provide output current up to 500mA and output voltage as low as 0.6V. The 10-bit D/A converter DAC6571 is available in a small 6-pin SOT23 package. The device is part of TI's single-channel D/A converter family DAC7571/6571/5571, which provides 12/10/8-bit resolution. The above products integrate an I 2 C interface to support standard/fast mode (maximum 400 kbps) and high-speed mode (maximum 3.4 Mbps). At power-on, the integrated reset power-on circuitry sets the output voltage to 0V.  In this application, the TPS62300 is powered directly from a single Li-Ion cell. The DAC6571 is powered from a regulated supply, in this case 2.85V. This supply voltage can be derived from another system rail. The architecture of the D/A converter is based on an R/2R resistor string and is specified to be monotonic by design. As far as the core supply voltage is concerned, there are two different modes of operation we need to consider: - Default output voltage: This voltage is valid after the DAC is reset and powered on at startup. As long as the DAC is not programmed via the I2C interface, its output voltage will remain at 0V. At this stage, the core voltage can be calculated by resistors R1 and R2 according to the equation given in Table 1 (Setting the default output voltage). - DAC controlled output voltage: In this mode, the D/A converter output voltage should be higher than 0.45V to take advantage of the "override" function. In this mode, the core voltage can be calculated according to the equation given in Table 1 (MOS1 high impedance). 
Figure 7 shows V DAC (DAC output voltage) versus VOUT (core voltage) depending on the DAC programmed value.  In this application, we have chosen the default core voltage of 1.3V. Therefore, the required resistor values for R1 and R2 should be: R1: 9.5kΩ
R 2 : 8.2kΩ Figure 8 shows the default core voltage regulation during power-up. The TPS62300 is powering a 3.9Ω resistive load, which results in a load current of 330mA at the 1.3V default output voltage. In Figure 8, the enable pin (EN) of the DC/DC converter is driven high along with V IN . The core voltage ramps up with minimal delay. However, new processors can generate control signals to enable the external core power circuitry themselves. In this case, the processor controls the enable pin of the TPS62300. The core voltage is ramped up to its system set value and the processor is running. The core voltage can be adjusted dynamically. In order to reduce power consumption and extend battery life, the processor clock and core voltage can be adjusted to the best.  in conclusion The dynamic voltage management solution supports fast and accurate voltage scaling required by current and next generation processor cores. It can be controlled through the I 2 C serial interface, which is a common interface for this purpose. The small packages of the TPS62300 and DAC6571 and the low number of external components enable an ultra-small solution size. The TPS62300 has the industry's best load and line transient performance, which makes the device ideal for the core power supply of the next generation processors. References: TI TPS62300 data sheet, 查看详情 ;
TI DAC6571 data sheet, 查看详情 . | (Conclusion of the full text | | 
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