Dual-channel 14-bit 65MSPS A/D converter AD13465 and its application

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Dual-channel 14-bit 65MSPS A/D converter AD13465 and its application [Copy link]

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1 Introduction Welcome to Wuyou Electronic Development Network ( Online Reading of Technical Articles Online Mall)
AD13465 is a dual-channel 14-bit A/D converter from Analog Device, which integrates amplifiers, voltage references, A/D converters and output components. The device has an on-chip tracking/holding circuit and adopts an improved multi-channel structure to provide excellent system performance. Its sampling rate reaches 65MHz. The device adopts advanced circuit design and laser-trimmed thin-film resistor network to obtain excellent channel matching and impedance control, and provides a variety of driving methods for analog input. The main types are single-ended, differential, and optional series filtering. In addition, users are provided with a choice of analog input signal ranges, which can further reduce additional external signal conditioning to a minimum, while still maintaining the versatility of the device. The analog signal conditioning circuit in this device uses a ±5.0V power supply voltage; the A/D conversion circuit uses a 5.0V power supply voltage; and the output stage circuit uses a 3.3V power supply voltage. In this device, each signal channel is completely independent and can use independent encoding and analog input, but still maintains minimal crosstalk and interference. 2 Performance characteristics and functional block diagram of
AD13465 2.1 Package appearance of AD13465

Figure 1 Package outline of AD13465

The package outline of AD13465 is shown in Figure 1, and the pin function is shown in Table 1. 2.2 Main features of
AD13465　　This device is a dual-channel 14-bit A/D converter with a minimum sampling rate of 65MHz, a matching gain error of ±1% between channels, an isolation of 90dB between channels, DC-coupled signal conditioning, a dynamic range of 85dB without false signals, selectable bipolar input with an input range of ±1V and ±0.5V, 3.3V compatible output, and a power consumption of 1.8W per channel.

Table 1 AD13465 pin functions

Pin Number	symbol	Function	Pin Number	symbol	Function
1,35	SHIELD	Internal ground shield between channels	34	DROUTA	A data waiting to be output
2, 3, 9, 10, 13, 16	AGNDA	A channel analog ground, A and B ground should be connected as close to the device as possible	36	DROUTB	B data waiting to be output
4	A-IN	Inverting differential input (gain = 1)	37-4245-52	D0B－D13B	Digital output of ADCB.D0 (LSB)
5	A＋IN	Non-inverting differential input (gain = 1)	43,44	DGNDB	B channel digital ground
6	AMP-OUT-A	Single-ended amplifier output (gain = 2)	53	DVCCB	B channel digital positive supply voltage (nominal 5.0V/3.3V)
7	AMP-IN-A-1	Analog input of the A-side ADC (±0.5V nominal)	54,57,60,61,67,68	AGNDB	Channel B analog ground
8	AMP-IN-A-2	Analog input of the A-side ADC (±1.0V nominal)	55	ENCB	Encode input; transition triggered on rising edge
11	AVEEA	A channel analog negative supply voltage (nominal -5.0V or -5.2V)	56	ENCB	Two's complement encoding; differential input
12	AVCCA	A channel analog positive supply voltage (nominal 5.0V)	58	AVCCB	B channel digital positive supply voltage (nominal 5.0V)
14	ENCA	Two's complement encoding; differential input	59	AVEEB	B channel digital negative power supply voltage (nominal -5.0V or -5.2V)
15	ENCA	Complement input; conversion triggered on rising edge	62	AMP-IN-B-2	B-side ADC analog input (±1.0V nominal)
17	DVCCA	A channel digital positive supply voltage (nominal 5.0V/3.3V)	63	AMP-IN-B-1	Analog input of the B-side ADC (±0.5V nominal)
18-2528-33	D0A－D13A	Digital output of ADCA.D0 (LSB)	64	AMP-OUT-B	Single-ended amplifier output (gain = 2)
26,27	DGNDA	Channel A digital ground	65	B＋IN	Non-inverting differential input (gain = 1)
			66	B-IN	Inverting differential input (gain = 1)

2.3 Performance Specifications of
AD13465 The performance specifications of AD13465 are shown in Table 2, where AVCC=5V; AVEE=-5V; DVCC=3.3V. 3 Working Principle and Usage of
AD13465 AD13465 is a pipeline structure dual-channel A/D converter. Each channel is composed of 4 monolithic integrated circuits (AD8037, AD8138, AD8031 and AD6644) of Analog Device and multiple passive resistor networks and decoupling capacitors. It has an input selection scheme, an input range of 1VP-P~2VP-P, and an input impedance of 50Ω, 100Ω and 200Ω. In the single-ended input terminal structure, the user selects the corresponding input terminal suitable for the application needs through the external, and the input signal passes through the precision resistor trimmed by laser to obtain a full-scale signal of ±0.5V or ±1.0V. The result of the voltage divider resistor is that a full-scale input of approximately 0.4V is applied to the non-inverting input of the AD8037 amplifier in the AD13465 input structure. The AD8037 amplifier has innovative structural features that can maximize the dynamic range of the amplifier's input and output. The AD8037 amplifier drives the AD8138 in the single-ended to differential amplifier, providing high input impedance and gain. The AD8138 has a 300MHz-3dB bandwidth, which can provide differential signals with the lowest harmonic distortion in differential amplification mode. Its differential output helps the differential input of the AD6644 to achieve balance so that the performance of the device can reach the best level. The AD8031 provides a buffer for the internal reference A/D converter, and the internal reference voltage of the AD6644 is designed to track offset and drift, and is used to ensure matching over an extended operating temperature range. The reference voltage is connected to the input of the AD8138 output common mode, which establishes the output common mode of the AD8138 at 2.4V. AD6644 has complementary analog input pins A+IN and A-IN. Each analog input is centered at 2.4V and has a swing of ±0.55V. Because A+IN and A-IN are 180-degree phase outputs, the differential analog input signal is 2.2VPP, and the two analog inputs are buffered before tracking/holding. The digital output of AD6644 drives a 100Ω series resistor, and the result is a 14-bit parallel CMOS-compatible digital number encoded as 2's complement. In order to facilitate single-ended input applications, multiple input structures are designed in the structure to allow users to select input signal levels and input impedance. The standard inputs are ±0.5V and ±1.0V, and users can select the input impedance of AD13465 for any input. The impedance pattern that can be obtained at each output position is: when AMP-IN-X-2 is open, AMP-IN-X-1=100Ω; when AMP-IN-X-2 is shorted to ground, AMP-IN-X-1=50Ω; when AMP-IN-X-1 is open, AMP-IN-X-1=100Ω. Each channel has two analog inputs: AMP-IN-A-1 and AMP-IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. When a full-scale input of ±5V is required, use AMP-IN-A-1 or AMP-IN-B-1; when a full-scale input of ±1V is required, use AMP-IN-A-2 or AMP-IN-B-2. Each channel has an AMP-OUT, which must be connected to the non-inverting or inverting input of the differential amplifier with the input grounded. For example, on the A side, AMP-OUT-A (pin 6) must be connected to A+IN (pin 5) together with A-IN (pin 4) connected to ground for non-inverting operation; or AMP-OUT-A (pin 6) must be connected to A+IN (pin 5) connected to ground together with A-IN (pin 4) for inverting operation.

Table 2 Performance specifications of AD13465

parameter	temperature	AD13465AZ/BZ			unit
parameter	temperature	Minimum	typical	maximum	unit
Resolution		14			Bit
DC accuracy No missing codes Offset error Offset error Channel matching	Full temperature 25℃ Full temperature Full temperature	Guarantee - 2.2 -2.2- 1.0	±0.2±1.0±0.1	+2.2+2.2+1.0	%FS% FS%FS
Gain Error Gain Error Channel Matching	25℃ Full temperature 25℃ Maximum and minimum	-3.0-5.0 +1.5- 3.0-5.0	-1.0±2.0± 0.5± 1.0±1.0	+1.0+5.0+1.5+3.0+5.0	%FS% FS% FS% FS%FS
Single-ended analog input Input voltage range AMP-IN-X-1 AMP-IN-X-2 Input resistance AMP-IN-X-1 AMP-IN-X-2 Input capacitance Analog input bandwidth	Full temperature Full temperature Full temperature Full temperature Full temperature	99198	±0.5±1.0100 2004.0100	1012027.0	VVΩΩp FMHz
Conversion Performance Highest Conversion Rate Lowest Conversion Rate Aperture Delay (tA) Aperture Instability (Deviation) Encoding Pulse with High Level Encoding Pulse with Low Level Output Delay (tOD) Encoding, Rise to Data Ready, Rise Delay	Full temperatureFull temperature25℃25℃25℃25℃Full temperatureFull temperature	655.05.0	1.50.37.77.77.511.5	209.59.5	MSPSMSPS nspsrms nsnsnsns
SNR (Signal/Noise Ratio) at 4.98MHz analog input at 9.9MHz analog input at 21MHz analog input at 32MHz	25℃25℃Full temperature25℃Full temperature25℃Full temperature	70696968	72727171707069		DBFSdBFSd BFSDBFS dBFSdBFS dBFS
Single-ended analog input achieves 10MHz passband ripple and 25MHz passband ripple	25℃25℃		0.050.10		dBdB
SINAD (Signal/Noise Plus Distortion) at 4.98MHz analog input at 9.9MHz analog input at 21MHz analog input at 32MHz	25℃25℃Full temperature 25℃ Full temperature 25℃ Full temperature	69.068.566. 566.0	72.072.070. 570. 069.063. 061.0		DBFSdBFSd BFSDBFSBF SdBFSdBFS

parameter	temperature	AD13465AZ/BZ			unit
parameter	temperature	Minimum	typical	maximum	unit
Encoder Input (ENC, ENC) Differential Input Voltage Differential Input Impedance Differential Input Capacitance	Full temperature 25℃25℃	0.4	102.5		VP－PkΩpF
Glitch-free dynamic range Analog input at 4.98MHz Analog input at 9.9MHz Analog input at 21MHz Analog input at 32MHz	25℃25℃Full temperature25℃Full temperature25℃Full temperature	80787069	8568476746362		DBFSdBFSdBFSdBFS dBFSdBFSdBFS
Differential analog input Analog signal input range A+IN to A-IN and B+IN to B-IN Input impedance Analog input bandwidth	Full temperature Full temperature Full temperature		±1.061850		VΩMHz
Differential analog input achieves 100MHz passband ripple and 25MHz passband ripple	25℃25℃		0.300.82		dBdB
Two-tone image suppression fin = 9.1MHz and 10.1MHz f1 and f2 are -7dB fin = 19.1MHz and 20.7MHz f1 and f2 are -7dB	25℃ Full temperature 25℃	77.576.5	828072		dBcdBc
Isolation between channels	25℃	90			dB
Transient response	25℃		15.3		ns
Digital Output Logic Compatibility DVCC = 3.3V Logic 1 Voltage Logic 0 Voltage DVCC = 5V Logic 1 Voltage Logic 0 Voltage Output Coding	Full temperature Full temperature Full temperature Full temperature	2.50.2	CMOSDVCC－0.20.5DVCC－0.30.352's complement		VVVV
Power Supply AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current Supply Current per Channel (Total) Power Consumption (Total) Power Supply Rejection Ratio (PSRR)	Full temperature full temperature full temperature full temperature full temperature full temperature full temperature full temperature full temperature	4.85－5.2853.135	5.0270－5.0383.33436 93.570.02	5.25308－4.75493.46546 4033.9	VmAVmAVmAm AW %FSR/%Vs

When used for differential input applications, each channel of the AD13465 is designed with two optional differential input structures: A+IN, A-IN and B+IN, B-IN. This input structure provides system designers with the ability to bypass the AD8037 amplifier and directly drive the AD8138. In the single-ended or differential input structure, the AD8138 differential ADC driver can be used. The differential analog input has a nominal input impedance of 620Ω and a nominal full-scale input range of 1.2VPP. The AD8138 amplifier drives a differential filter and a custom A/D converter. The differential input structure provides the lowest even harmonics and signal/noise (SNR) performance, and its performance reaches 3dB (SNR=73dB). When laying out the differential input signal channel, special care should be taken. The differential input transmission line characteristics should be matched and balanced. Similarly, in the system signal channel, attention must be paid to the structural layout in order to obtain a large performance improvement.

Figure 2 Crystal clock oscillator - differential encoding application circuit

Figure 3 ECL/PECL differential coupling circuit for encoding

When applying AD13465, in order to prevent its performance from degrading, the encoding signal must be a high-quality, extremely low phase noise source signal. To maintain 14-bit accuracy at 65MSPS, special attention must be paid to the encoding clock phase noise. When using a high-dither clock source, the SNR performance at a 32MHz input signal will easily decay from 3dB to 4dB. In order to obtain the best performance, AD13465 must use a different clock signal. The encoding signal is usually AC-coupled to the ENCODE and ENCODE pins through a transformer or capacitor. These pins are internally biased and do not require external bias.
Figure 2 shows the circuit application connection method, which is a preferred method for adding clock to AD13465. Among them, an RF transformer is used to transform the clock source from a single-ended to a differential signal, and two reverse-connected Schottky diodes are connected across the two ends of the secondary coil of the transformer to limit the clock offset so that the AD13465 is close to the 0.8VP-P differential level. This method helps prevent the clock fed back to other parts of the AD13465 from generating large voltage swings and limits the noise signal present at the ENCODE input. A crystal oscillator can also be used to drive the RF transformer if an appropriate series limiting resistor (typically 100Ω) is used on the secondary coil. If a very low-jitter ECL/PECL clock is available (Motorola's MC100LVEL16 device provides excellent jitter performance), the ECL/PECL differential signal can be AC-coupled to the encoder input pins as shown in Figure 3.
Be particularly careful when selecting the power supply, because linear power supplies are strongly required to work under command control, and switching power supplies may cause the AD13465 to receive radiated signals. Each power supply pin should be decoupled with a 0.1μm chip capacitor and connected as close to the package as possible.
The AD13465 has independent digital power and analog power supply pins, where AVCC is the analog power supply and DVCC is the digital power supply. They are independent of each other. Otherwise, the fast alternating digital output signal will couple the switching current back to the analog power supply. When applying, it is necessary to pay attention to AVCC to be kept within +5% and -3% of 5V, and DVCC = 3V, because 3V is the common power supply voltage of ASIC.
When designing the data receiver of AD13465, it is also necessary to be careful that the digital output signal drives the internal series resistor (for example, 100Ω), followed by a gate circuit, such as 75LCX574. In order to minimize the capacitive load, each output pin can only be connected to one gate circuit. The digital output signal of AD13465 has a constant output slew rate of 1V/ns. The typical CMOS gate circuit combined with the circuit wiring of the PCB will have a load of 10pF. Therefore, during the switching process of each bit, there will be a dynamic current of 10mA (10pF×1V÷1ns) flowing at the input or output of the device, so the full-scale conversion may cause a transient current of up to 140mA (14 bits×10mA/bit) to flow into the output stage. This switching current is limited between ground and the DVCC pin. Standard TTL gates should be avoided as they will significantly increase the dynamic switching current of the AD13465. It should also be noted that external capacitive loads will increase the output time and invalidate the timing specification. Digital output timing is guaranteed with a 10pF load.
When designing for high frequency/high resolution applications, it is recommended to use high quality ceramic chip capacitors as decoupling capacitors directly from the device power pins to ground. All capacitors can use standard high quality ceramic chip capacitors.
Be careful when setting up digital output operation. Due to the high slew rate of the digital output, the capacitive loading of the digital output should be minimized. The circuit connections to the digital output should be kept short and should be connected directly to the receiving gate circuit. The internal circuit buffers the output of the ADC through a resistor network, which can eliminate the need for external isolation measures between the device and the receiving gate circuit.
4 Application fields of
　　AD13465 AD13465 is a wide dynamic range 14-bit 65MHz dual-channel A/D converter. This device can be used in radar signal processing (I/Q baseband working signal optimization), phased array receivers, multi-channel multi-mode receivers, GPS anti-interference receivers, communication receivers and other fields. SOC development platform 360 yuan Deluxe microcontroller development system 498 yuan Microcontroller learning board 138 Wireless nRF-9E5 module 100 yuan 51 Microcontroller test development board 230 yuan Genius NSP universal programmer 2 60 yuan Mini ARM Debugger 330 yuan LABTOOL-48UXP 2800 yuan S3C2410 ARM9 development board 800
5 Conclusion
This device is a high-speed, high-precision, wide dynamic range A/D converter with excellent performance and easy use. It is a good choice for high-speed signal processing systems.