Sine wave output DC/AC power supply based on DSP 56F801

破茧佼龙

Sine wave output DC/AC power supply based on DSP 56F801 [Copy link]

At present, low-power DC/AC power supplies have been widely used in UPS and renewable energy fields (such as photovoltaic household power supplies).

The function of this type of power supply is to convert low voltage DC into AC power.

The main circuit structure of this type of power supply is composed of high-frequency DC/DC and DC/AC (inverter). Output waveform and conversion efficiency are important indicators for measuring this type of product, and one of the keys to ensuring these indicators is the design of its controller.

This paper introduces a DC/AC power supply design based on the cost-effective 16-bit digital signal controller DSP 56F801 and pulse width modulation chip UC3846. The design realizes the generation of control signals and the detection of measurement signals in the device, and adopts digital control of voltage effective value feedback plus pre-filter PID regulator and anti-interference measures combining hardware and software. The experimental results show that the output waveform, efficiency and reliability of the DC/AC power supply of this design have been improved.

1 Main circuit working principle

Figure 1 shows the main circuit structure of the design, in which the DC voltage of the 24V battery is boosted to a DC high voltage of 360V through the switch tubes S1 and S2 , the high-frequency transformer T, the bridge rectifier, L1 and C1, and then passes through the inverter bridge composed of S3~S6 to obtain an AC output of 220V/50 Hz.

1.1 DC/DC Link

The primary inverter circuit topologies in the boost DC/DC link using a transformer include half-bridge, full-bridge, push-pull, etc. The output level of the half-bridge circuit can only be half of the battery voltage. Since the full-bridge circuit has two tube voltage drops in its conduction loop, using these two circuit topologies in a low DC voltage loop will limit the efficiency of the device. The push-pull structure can make full use of the battery voltage, and there is only one tube voltage drop in the conduction loop, so this design uses a push-pull structure.

In each cycle of the push-pull converter , S1 and S2 are turned on once in their respective half cycles. In order to prevent the transformer from being magnetized, the time for S1 and S2 to be turned on alternately should be equal, and the winding of the center tap winding on the primary side of the transformer should be symmetrical.

The secondary side of the transformer boosts the AC voltage generated by coupling with the primary side, and then obtains a high-voltage DC voltage through uncontrolled rectification. The DC voltage relationship in the DC/DC link is described by equation (1).

Where: VDC1 is the battery voltage;

VDC2 is the output voltage of the DC/DC link;

N2 is the number of turns on the secondary side;

N1 is the number of turns on the original side;

D is the duty cycle[1].

1.2 DC/AC Link

The main circuit of the DC/AC converter is a single-phase bridge inverter circuit composed of 4 MOS tubes, which converts 360V DC voltage into 220V/50Hz AC voltage.

SPWM modulation is divided into two types: non-frequency doubling and frequency doubling. This paper adopts a frequency doubling unipolar SPWM modulated inverter. This method can control the gate pulse without changing the operating frequency of the switch tube, so that the lowest harmonic frequency in the output waveform is twice the switching frequency, thereby reducing the capacity and volume of the filter. There are two methods to generate a single-phase unipolar frequency doubling modulation drive signal. One is to use two sine waves with the same frequency and amplitude but opposite phases and a triangular carrier with a frequency of fc to intersect [1]. The other is to use two triangular carriers with the same frequency and amplitude but opposite phases and a sine wave to intersect. The result is two sets of PWM drive signals, which control the two arms of the single-phase inverter bridge respectively. The equivalent carrier frequency of the inverter output waveform is 2 fc. This paper adopts the former scheme.

2 Power supply control structure

The DC/DC link is controlled by the current-controlled pulse width modulator chip UC3846. This chip supports a dual-loop control structure that can achieve functions such as output voltage regulation, pulse-by-pulse current limiting, symmetry correction, and parallel connection of multiple power modules [2][3]. The DC/DC link is set to an operating frequency of 50 kHz by the external RC components of UC3846 .

In this design, the output voltage VDC2 of the DC/DC link is measured to form a voltage outer loop. At the same time, a current transformer is placed on the input bus of the transformer T to measure the current flowing through the main switch tube to form a current inner loop. UC3846 forms a double closed-loop structure to adjust ton to maintain the stability of VDC2. UC3846 can easily set the output voltage on the high-voltage side of the DC/DC link and the current limit value on the low-voltage side through its external components .

MOTOROLA's 56F801 is a 16-bit digital signal controller (DSC) chip that integrates the rich and flexible peripherals of the digital signal processor (DSP) and the microcontroller into one chip. The three execution units that can operate in parallel perform six operations in one instruction cycle, providing a low-cost solution for a variety of applications. One of its outstanding features is that it provides PWM and ADC modules to support multi-motor or multi-phase control. The PWM module of 56F801 generates SPWM signals conveniently and concisely without occupying timer resources. In this design, the chip generates PWM drive signals of S3~S6 in the DC/AC link, and monitors the entire device at the same time, performing measurement and control tasks.

3 Generation of SPWM pulse width modulation wave

The implementation of frequency-doubled SPWM is accomplished through the PWM module of 56F801. This module has 6 PWM pins and can support 3 pairs of complementary PWM signal outputs with inserted dead zones. In the design of the single-phase DC/AC link, two pairs of the 3 pairs of complementary PWM signals are used to drive S3 ~S6. The design points can be briefly described as follows.

Set the control register PMCTL and configuration register PMCFG, set the prescaler factor to 1 and the pulse width generation to center alignment.

If the triangular carrier signal frequency is set to 9.6 kHz, when the IPBus clock is 40 MHz and the pre-scaling factor is 1, the modulus value stored in the register PWMCM in the PWM module is [PWMCM] = 40M/9.6k/2 = 2084.

To prevent the two tubes on one bridge arm from being directly connected, a 2μs dead time is set by setting the pulse dead zone register PMDEADTM.

The value of PWMCM determines the pulse cycle, while the value in PWMVAL represents the pulse width. Together, they control the 15-bit counter PWMCNT to form a PWM waveform. In order to generate an SPWM drive signal, an interrupt must be generated in each cycle and the value in PWMVAL must be refreshed in the interrupt service.

The pulse width of this cycle is obtained by searching a pulse width table stored in a random access memory and assigning a value to PWMVAL. The process of looking up and assigning values to PWMVAL cycle by cycle is called cycle parameter reloading. The frequency of parameter reloading is determined by the frequency and pre-division factor of the PWM module and the frequency of the carrier. Figure 3 is a flow chart of outputting double-frequency SPWM pulses. The value of the neutral point in Figure 3 is F=1042, which is half of the carrier triangle wave period. The sine table pointer is PWMPTR.

4 56F801 Software Design

The 56F801 software mainly consists of the main program, parameter loading interrupt of the PWM module, timing interrupt of output voltage filtering and closed-loop regulation, and related protection interrupts.

The main program mainly completes the initialization of related registers and variables, and forms the operating environment of each interrupt-based functional module.

The parameter reload interrupt of the PWM module completes the output of the PWM wave.

As shown in Figure 2, 56F801 detects the battery and DC/AC links and performs corresponding protection, including the interrupt caused by the error protection pin of the PWM module. This interrupt completes the short-circuit protection function.

The power supply device is also equipped with under-voltage and over-voltage hysteresis protection on the DC input side implemented by UC3846, and overload, short-circuit and overheat protection on the AC output side implemented by 56F801. When the DC input side is over-voltage or under-voltage, the PWM waveform generator is turned off through the interlocking signal, and the DC/DC converter is blocked at the same time. When overloaded, a delay is first made, and then the PWM generator is turned off and the DC/DC is blocked. However, if the load returns to normal during the delay period, the entire system automatically resets and starts working.

The above-mentioned pulse width table is offline for the SPWM generation module, but is online for the voltage closed-loop control module.

The voltage closed-loop control module calculates the control quantity. The change of the control quantity changes the intersection of the sine modulation wave and the triangle wave, which leads to the refresh of the pulse width table. To this end, it is necessary to calculate the pulse width of each SPWM wave in a sine wave cycle according to the symmetrical regular sampling method of the modulation wave and the triangle carrier, and arrange a table in the memory to store the pulse width value of each pulse.

This system adopts a single closed-loop feedback control scheme of effective value, and its control structure is shown in Figure 4.

The regulator running in 56F801 uses a pre-filter PID algorithm. Since high-frequency interference in the sampling circuit may cause control errors, a first-order lag filter is used as a pre-filter at the front end of the PID. This method first filters the collected error signal with a first-order lag digital filter to obtain a more accurate error sampling value Ek, which is then sent to the PID controller to obtain the control output Δ Uk.

The transfer function of the first-order lag filter is

Where: e(s) is the actual error sampling value containing high-frequency interference;

E(s) is the error after filtering with high-frequency interference eliminated.

The difference equation discretized by the difference inversion method is:

Where: ek is the deviation sampling value of this time;

Ek and Ek-1 are the current and last filtering values.

In formula ( 3),

Where: Т is the filtering time constant;

T is the sampling period.

Digital PID uses an incremental algorithm to

The use of formula ( 6) can simplify the computer operation:

Uk can be obtained according to Δ Uk, and then a new pulse width table can be obtained, and the relevant storage area can be refreshed.

Figure 5 Test waveform

5 Experimental results and conclusions

Based on the above scheme, a prototype was manufactured and relevant tests were carried out. Considering that the load powered by this type of power supply is generally a capacitive load such as a switching power supply, pure resistive load and switching power supply capacitive load tests were carried out respectively.

Test parameters: battery DC voltage 24V; DC/DC converter output DC 360V; DC/AC link triangle carrier frequency 9.6kHz, sinusoidal modulation wave frequency 50Hz, modulation ratio M=0.9; DC side capacitor C1=1000μF; output filter inductor L2=2mH, filter capacitor C2=5μF.

The test waveform results show that the DC voltage output by the DC/DC converter has small fluctuations. Due to the use of the DSP56F801 control chip , the output waveform has small waveform distortion even when the load is capacitive, and the waveform quality is high. The harmonic distortion (THD) of the output waveform is tested to be 0.9% when no-load, 1.8% when resistive load, and 2.6% when switching power supply load.

The prototype is very small. The reliability of the whole system is enhanced by taking anti-interference measures for software and hardware.