Analog/digital mixed circuit acceleration simulation technology

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Analog/digital mixed circuit acceleration simulation technology [Copy link]

Analog/digital mixed circuit acceleration simulation technology

[Source: Electronic Engineering Journal] [Author: Lu Zhenting, Song Lei] [Time: 2006-1-17 9:14:21] [Clicks: 90]

Introduction to Fast SPICE Technology In order to overcome the shortcomings of the first generation of SPICE simulation tools (such as Spectre and PSPICE) in simulation capacity (about 50K) and speed, the second generation of SPICE technology, namely Fast SPICE simulator, adopts circuit partitioning, multi-rate, simplified model and other accelerated simulation technologies. Traditional SPICE simulator treats the circuit as a matrix. As the circuit scale increases, the matrix solution speed decreases significantly. Fast SPICE puts related circuit modules together and divides the large matrix into many small matrices to reduce the amount of calculation. In addition, event-driven technology can ignore inactive circuits and further reduce the amount of calculation. Another advantage of circuit partitioning is that multi-rate simulation can be used. Each circuit module often has different operating frequencies, so different circuit blocks in the simulation can use different simulation steps. In this way, it can ensure that the high-frequency circuit obtains accurate results, and the low-frequency modules can avoid repeated calculations and reduce the CPU load. Simplified model technology is another important technology for Fast SPICE acceleration. In traditional circuit simulation, MOSFET or BJT requires a set of complex formulas for calculation, which often consumes a lot of CPU time. Fast SPICE generates a model table at the beginning of the simulation, and then performs a table lookup, which saves a lot of time. Fast SPICE can meet different accuracy and speed requirements through multi-level simplified models. Figure 3: Post-layout simulation flow and RC stitching technique. As a new generation of Fast SPICE simulator, Virtuoso UltraSim Simulator introduces hierarchical homogeneous simulation, dynamic circuit segmentation and other technologies. For the same submodules in the circuit, only one needs to be calculated to avoid repeated calculations, thereby further improving the simulation capacity and speed; providing full compatibility with traditional SPICE and simulation accuracy similar to SPICE; simple options allow designers to easily customize circuit simulation; improved RC reduction technology enables accurate and fast post-simulation. In addition, UltraSim has been fully integrated into the Cadence standard analog design flow. These advantages make UltraSim one of the most widely used Fast SPICE tools in the industry. 1. Accurate model support Silicon-accurate device models have always been the key to accurate circuit simulation and physical effect analysis. By sharing all models and formulas with BSIMPro+, an industry-recognized advanced device model extraction tool, UltraSim not only has powerful device model support capabilities, but also ensures silicon-accurate simulation results. 2. Intrinsic compatibility Various simulators in Cadence MMSIM (including Spectre, SpectreRF, AMS Designer and UltraSim) read device models through CMI and use the same VerilogA engine, eliminating the inaccuracy and instability caused by incompatible simulators (as shown in Figure 2). In addition, as a mixed-signal simulator, UltraSim supports Spectre, structured Verilog and various SPICE netlists; supports all standard models and model units that describe specific circuits (such as flash macro models), behavioral description languages VerilogA and SpectreHDL; supports VCD/EVCD/VEC; supports traditional SPICE post-processing methods (such as .measure, various waveform file formats, etc.). 3. Powerful post-simulation capabilities Because a large number of parasitic resistors and capacitors (RC) are introduced, post-simulation is more challenging. UltraSim uses a dedicated RC reduction technology to effectively reduce the number of RCs (up to 90%) and control the accuracy loss within 1% to 3%. Compared with traditional RC reduction technology, UltraSim's patented algorithm can significantly reduce simulation time and memory consumption while ensuring accuracy. The RC reduction technology used by UltraSim does not simply filter small capacitors or resistors, but replaces the original complex RC network with a simplified equivalent RC network, and can automatically adjust the simplification degree of RC according to the signal frequency. Table 1: Comparison of Spectre and UltraSim simulation results for ∑-Δ ADC. UltraSim supports all standard post-layout netlist formats, such as SPICE netlist, Extracted View, flat or hierarchical DSPF or SPEF netlist, DPF, and node capacitance netlist, etc., and supports a variety of post-simulation processes in the industry. In addition, UltraSim's RC stitching technology can selectively add parasitic RC to specified circuit modules (as shown in Figure 3), allowing designers to flexibly customize their circuit simulation processes, such as using behavioral models for certain digital modules and using netlists with parasitic parameters for certain important analog modules. UltraSim provides a postl option to set the degree of simplification of RC reduction, which can automatically adjust all relevant RC compression parameters. Experienced designers can also freely adjust various parameters as needed. 4. Simulation ease of use The simulation accuracy of analog/digital mixed circuits depends on the model accuracy and simulator tolerance. When using UltraSim, designers generally only need to set the simulation mode and speed to optimize the simulation and achieve a good match between accuracy and speed. Of course, experienced designers can adjust various options based on their understanding of their design and Fast SPICE technology to further improve simulation performance. UltraSim has been fully integrated into the Cadence standard full-custom design flow. Users can easily switch between different simulators such as Spectre, UltraSim and AMS Designer in ADE to complete simulation and debugging from module-level circuits to full-chips. In the ADE interface, designers can generate Spectre or standard SPICE netlists as needed, and quickly set simulation mode and speed options in a graphical manner to obtain good accuracy and speed matching. In addition, ADE also provides a friendly interface for UltraSim's timing, power consumption, and reliability analysis. 5. Power network analysis, design checks, and others For circuits containing power networks, the presence of resistor networks will reduce simulation speed. For this reason, UltraSim has launched a UPS solution, which separates the power resistor network from other circuits and is simulated by UPS and UltraSim in collaboration. Therefore, while obtaining 3-5 times accelerated simulation, accurate IR voltage drop analysis reports can still be obtained. In order to find and modify errors in the design, UltraSim provides a variety of design checking functions, including overload current checking, voltage crossing checking, high resistance node checking, DC leakage current path checking, etc. Ultrasim's timing analysis tool can help designers detect errors in conversion time, setup time, hold time or pulse width, while the power analysis tool can report the current and power consumption at the specified time and the specified sub-circuit port. For high-frequency circuits, Ultrasim provides Fast Envelope simulation, etc. Simulation Examples The following section uses two typical examples to illustrate how to use UltraSim to simulate analog/digital mixed circuits. 1. ∑-Δ ADC Compared with Nyquist sampling ADC, oversampling ADC contains fewer analog devices, but due to the high oversampling rate, it often requires a longer transient simulation time. This example is the post-simulation of a ∑-Δ ADC. The circuit has a maximum internal clock frequency of 450MHz, contains 1 VerilogA module, a transient analysis time of 20us, and 4,751 FFT analysis sampling points. Table 1 compares the simulation results of Spectre and UltraSim. Table 2: Device statistics before and after RC reduction. Here, the simulation options are set to sim_mode=MS (the global mode of analog/mixed-analog circuits generally uses the default MS mode) and speed=1 (defines the tolerance of the simulator, equivalent to Spectre's Moderate mode). To ensure simulation accuracy, the post-simulation uses the default value (postl=1), which is a more conservative RC reduction technique. As can be seen from Table 2, after RC reduction, the number of capacitors is reduced from 60.7K to 1.3K, of which the number of coupling capacitors is only 529. Due to the use of hierarchical and isomorphic techniques, the number of juncaps is reduced from 27K to 2.11K. Ultimately, UltraSim achieves an 11-fold speed increase. 2. RF PLL This example is a PLL for wireless communication. Its pre-simulation netlist contains 31K MOSFETs, 600BJTs, 75K diodes, and approximately 1.5KR/C. The reference clock frequency is 33MHz, and the LC-type VCO frequency is 3.9GHz. The UltraSim reference settings are: .usim_opt sim_mode=ms speed=5 analog=3 .usim_opt speed=4 method=gear2 IPLL.VCO .usim_opt sim_mode=df IPLL.LOGICHere , we use the MS simulation mode, where analog=3 makes UltraSim consider a larger feedback loop when dividing the circuit to ensure accuracy; speed=4, method=gear2 is applied locally to the VCO module (usually RF VCO requires the use of gear or trap convergence algorithms and smaller tolerances). The digital module uses the df mode, which uses a simplified digital table model to further improve the speed. UltraSim completed the 25us transient simulation in just 19 hours, even exceeding the designer's expectations. .