74hc4046 loop filter design

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74hc4046 loop filter design [Copy link]

When designing 74HC4046 with PLLsim, what is the appropriate charge pump current Icp and VCO control sensitivity Kv? Please help.

gmchen

There are several problems, let's solve them one by one.

1. The 74HC4046 has three phase detectors, namely, XOR gate, JK trigger and phase frequency detector (PFD), which are marked as PC1, PC3 and PC2 on the device. PC1 and PC3 are directly high and low level outputs, so there is no charge pump problem. PC2 (phase frequency detector) is a three-state output, but it is not a charge pump output, but three output states: high level, low level, and high impedance. The chip does not provide a place to set the output current. So the original poster's question is not valid.

The 4046 with charge pump output is its improved version, model 9046. It seems that this chip is rarely seen.

There are also some PLL chips with charge pump output, such as ADF4001, which rely on internal registers to set the charge pump current.

gmchen

Question 2: VCO control sensitivity.

The VCO of HC4046 is a current-controlled RC relaxation oscillator, whose control current is determined by two external resistors. One resistor (pin 12) provides a fixed bias current, and the other resistor (pin 11) provides a current controlled by the control voltage. These currents and the timing capacitor together determine the controlled oscillation frequency of the VCO, including the oscillation center frequency and the oscillation frequency range. This center frequency and frequency range basically determine the voltage control sensitivity of the VCO.

However, this center frequency and frequency range are constrained by the PLL working target. For example, if a frequency synthesizer is to be made, the output frequency range of the frequency synthesizer is predetermined, and the oscillation frequency range of the VCO cannot be less than the required frequency range of the frequency synthesizer. Since the control voltage range of the VCO is roughly determined (after the power supply voltage is determined), the larger the oscillation frequency range of the VCO, the greater the control sensitivity, so the voltage control sensitivity of the VCO cannot be specified casually by the designer. In the above example, the voltage control sensitivity of the VCO can be larger, but too large a voltage control sensitivity will increase the output phase noise, so the appropriate voltage control gain should be selected under the condition of meeting the requirements.

gmchen

Third, the original poster started to talk about using PLLsim to design 74HC4046.

Is this a simulation software? I have never used it, and I don't know its design process. All the answers above are based on the actual circuit composed of the actual 74HC4046 chip.

Usually when designing a phase-locked loop circuit for an actual application chip, my approach is: first determine the VCO's oscillation center frequency and oscillation frequency range based on actual needs, so that the voltage-controlled gain is determined. Then select the phase detector based on actual needs, and in most cases, the PFD (PC2 of the chip) will be selected, and then the loop filter can be designed. Basically, once the loop filter is designed, a phase-locked loop application circuit is also designed, and the design of the rest of the parts is mostly simple.

gmchen

I have a series of posts about phase-locked loops on this website. The address of the first post is https://en.eeworld.com/bbs/thread-607483-1-1.html, which can be used for reference.

3388688476

gmchen posted on 2024-7-10 13:16 I have a series of posts about phase-locked loops on this website. The address of the first post is https://en.eeworld.com/bbs/thread-607483-1-1 ...

Thank you. Thank you.