Quasi-bidirectional port/weak pull-up mode of microcontroller

乱世煮酒论天下

Quasi-bidirectional port/weak pull-up mode of microcontroller [Copy link]

According to the analysis of this picture, the upper circuit is the output, and the lower circuit is the input, which is a quasi-bidirectional input and output port.

When the port outputs, assuming it is a high level, it passes through two NOT gates and two CPU signal delays to reach the OR gate. Why are two CPU clock signal delays used here? After the OR gate output is still a high level, at this time, one output signal is divided into two paths to drive two MOS tubes to conduct, and the output is a high level. Similarly, the output can be a low level. I wonder if my understanding is correct?

If it is configured as a port input state, then it is the input circuit below. The following one should be relatively simple, with a Schmitt trigger flipping the level, which has a certain debounce capability. Assuming that the external input is high level, it is low level after the Schmitt trigger, but what is the role of the MOS tube connected to the back stage of the Schmitt trigger, and what does weak mean?