Measured at 52.4MB/s! CSI communication case study of domestically produced ARM+FPGA!

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Measured at 52.4MB/s! CSI communication case study of domestically produced ARM+FPGA! [Copy link]

CSI Bus Introduction and Advantages

The CSI (CMOS sensor parallel interfaces) bus is a parallel communication interface used to connect image sensors and processors. It is used in industrial automation, energy and power, smart medical care and other fields. The schematic diagram of the CSI bus interface is shown below (taking the CSI0 of the Allwinner Technology T3 processor as an example).

figure 1

High bandwidth : The CSI bus supports high-speed data transmission and can meet the transmission requirements of multi-channel high-speed AD data.

Easy development difficulty : The CSI bus uses a parallel data and control signal separation method, with simple timing and low difficulty in FPGA-side interface development.

Low cost : The CSI bus uses parallel transmission, which uses fewer resources on the FPGA side and has low requirements on FPGA device resources.

Introduction and advantages of domestic ARM + FPGA architecture

In recent years, with the continuous advancement of China's new infrastructure and Made in China 2025 plans, single ARM processors are increasingly unable to meet the functional requirements of industrial sites, especially in today's energy and power, industrial control, smart medical and other industries, which often require ARM + FPGA architecture processor platforms to achieve specific functions such as multi-channel/high-speed AD acquisition, multi-channel network ports, multi-channel serial ports, multi-channel/high-speed parallel DI/DO, high-speed data parallel processing, etc. Therefore, ARM + FPGA architecture processor platforms are becoming more and more popular in the market.

figure 2

Chuanglong Technology SOM-TLT3F is a heterogeneous multi-core domestic industrial core board based on Allwinner Technology T3 quad-core ARM Cortex-A7 processor + Unisplendour Tongchuang Logos PGL25G/PGL50G FPGA design. The ARM Cortex-A7 processing unit has a main frequency of up to 1.2GHz. All components such as the core board ARM, FPGA, ROM, RAM, power supply, crystal oscillator, connector, etc. are domestically produced industrial-grade solutions, with a localization rate of 100%.

Allwinner T3 is a quasi-automotive grade chip with a quad-core ARM Cortex-A7 architecture and a main frequency of up to 1.2GHz. It supports dual-channel network ports, eight-channel UART, and SATA large-capacity storage interfaces. It also supports 4-channel display, GPU, and 1080P H.264 video hardware codec. In addition, Chuanglong Technology has adapted the domestic embedded system SylixOS on the T3 platform, truly realizing the localization of software and hardware.

Unigroup Tongchuang Logos PGL25G/PGL50G FPGA is widely used in the industrial field. Its logic resources are 27072/51360 respectively. It is pin-to-pin compatible with foreign friendly products and is mainly used for multi-channel/high-speed AD acquisition or interface expansion. It is widely praised by industrial users for its low price, stable quality, and easy-to-use development environment.

Figure 3 Typical application areas of ARM + FPGA

Introduction to CSI communication case of domestic ARM + FPGA

This chapter mainly introduces the ARM + FPGA communication solution based on CSI between Allwinner Technology T3 and Unigroup Logos. The hardware platform used is: Chuanglong Technology TLT3F-EVM industrial evaluation board.

To simplify the description, the text only contains the functional description and test results of the solution. Please scan the QR code at the end of the text to download the detailed development document.

This example implements the CSI communication function between T3 (ARM Cortex-A7) and FPGA. The CSI0 bus used in the example supports a maximum resolution of 1080P@30fps and a data bit width of 8 bits, as shown in the figure below. The theoretical transmission bandwidth of CSI0 is: 1920 x 1080 x 8bit x 30fps ≈ 59MB/s.

Figure 4

The functional block diagram and program flow chart are shown below.

Figure 5 Functional block diagram

Figure 6 ARM program flow chart

ARM side case csi_test case description

The main functions of the ARM case csi_test are as follows:

(1) Based on Linux subsystem V4L2;

(2) Collect the specified number of frames of data through the CSI bus;

(3) Calculate the total time required;

(4) Print the average acquisition rate and verify the data of the last frame of the image.

FPGA-side case parallel_csi_tx case description

The main functions of the FPGA-side case parallel_csi_tx are as follows:

(1) Write the test data (0x00~0xFF) into FIFO;

(2) Data is read from the FIFO and sent to the ARM via the CSI bus in rows and frames with a resolution of 1024x512.

Case test demonstration

The FPGA program sets CSI_PCLK to 65MHz, and the clock FIFO_WR_CLK for writing test data to FIFO is set to 59MHz. Since the FPGA side needs to write data to FIFO and then read it out from FIFO and send it, the interval time between each line and each frame will be affected by the FIFO write rate, so the actual theoretical transmission bandwidth of CSI communication should be: (59MHz x 8bit / 8)MB/s = 59MB/s. As can be seen from the above figure, the actual measured transmission rate is about 52.4MB/s, and the bit error rate is 0, which is close to the theoretical communication rate.

Figure 7