Abstract: Using EDA tools and hardware description language (HDL) to design a high-performance-price-performance system-on-chip according to the specific requirements of the product is a method widely used internationally. Unlike traditional design methods, at the beginning of the design, it is not necessary to have a specific single-chip microcontroller (MCU) and development system (emulator) and a circuit board with peripheral circuits for debugging. All that is needed is the HDL module of the MCU core and various peripheral devices described in HDL provided by the integrated circuit manufacturer. In the virtual environment provided by the EDA tool, designers can not only write and debug assembly programs, but also use HDL to design, simulate and debug fast algorithm circuits and interfaces with their own characteristics, and automatically convert them into circuit structures through synthesis and wiring tools, corresponding to the manufacturer's cell library, macro library and hard core. After simulation verification, they can be put into production as a dedicated system-on-chip (SOC) integrated circuit.
Keywords: System on Chip (SOC) EDA Hardware Description Language (HDL) Single Chip Microcomputer
1. Chip design and manufacturing are the foundation of the development of the electronics industry.
In the past 10 years, China's electronics industry has made great progress. Whether in consumer products such as televisions and video recorders or in communication products such as telephones and network equipment, the quality and output of products have increased rapidly. However, the core components of these products, chips, mostly need to be imported, and a large amount of foreign exchange is required to purchase them every year. The improvement of the technical level of many products is also restricted by chips. Since the new chips used in high-end products are expensive, it is very difficult to develop electronic products and equipment that can compete in the international high-end product market. Most of the electronic products that can compete in the international market are still medium and low-end. Since most of the core chips need to be imported, the profit is very low, and they can only survive in the market by relying on China's relatively cheap labor. In the first five years of the 21st century, if we still cannot master the design and manufacturing technology of core chips, it will be difficult for the electronics industry to catch up with the international advanced level within 20 years. The design of core chips is an advanced technology, but not every core chip is very difficult to design and manufacture. The system on chip (SOC) in most low-end and medium-end electronic products is not complicated. At present, many electronic engineers in China have mastered the traditional means of microcontroller system development: writing assembly programs and using development systems for simulation to debug assembly programs and interface signals. On this basis, if you master some commonly used EDA tools, understand the design ideas of complex digital systems and can actively and deeply learn HDL language, you can not only design microcontrollers and circuit boards with your own intellectual property rights, but also design dedicated digital signal processing chips and systems on chip with tens of thousands or even millions of gates.
2. Mastering HDL is the stepping stone to using EDA tools to develop systems on chips .
Due to the complexity of the design, there must be a language that can accurately model various circuit behaviors and structures at all levels so that the design can be simulated on the computer to see if it is correct. HDL, especially Verilog HDL, is particularly favored by design engineers working on the front line, not only because HDL is very similar to C language and it is not difficult to learn and master it, but more importantly, it has shown extraordinary performance and scalability in the design of complex SOCs. In the field of simulation of digital system design, HDL has been widely recognized by digital system design engineers around the world more than 10 years ago and is currently the most popular hardware description language in the world. In particular, in recent years, it has also shown its vigorous vitality in the field of automatic synthesis of digital systems. Verilog HDL also supports the design of analog circuits. The Open Verilog International (hereinafter referred to as OVI) organization has recently published a draft of the Verilog-AMS Language Reference Manual (hereinafter referred to as LRM), which defines this hardware description language that can be used for analog and digital mixed signal system design. The Verilog-AMS hardware description language is a subset of the Verilog HDL that complies with the IEEE 1364 standard. It covers the definition and semantics of the Verilog HDL recommended by the OVI organization, with the aim of allowing designers of digital-analog mixed signal integrated circuits to create and use modules using both structural descriptions and high-level behavioral descriptions. Therefore, using the Verilog HDL language allows designers to use different levels of abstraction at different stages of the entire design process (from analysis and comparison of structural schemes to the implementation of physical devices). At present, with the efforts of many software companies, many model development tools are emerging, which will greatly speed up the model development process. They provide development tools for analog circuit models, such as circuit analysis tools, behavioral modeling tools, design optimization tools and design automation tools. Some tools can generate behavioral models of circuit components, which can be used for circuit simulation. Readers and electronic engineers with associative ability can easily imagine that they are indeed the product of revolutionary changes in design methods through the continuous emergence of new electronic products such as mobile phones and business communication.
3. The design of SOC should start with digital systems and gradually transition to digital-analog hybrid systems.
Since the basic components of digital systems are relatively simple, they are nothing more than some AND gates, OR gates, NOT gates, triggers, multiplexers, etc., and macro devices are nothing more than some adders, multipliers, etc. EDA tools for designing digital systems are also relatively easy to get for free. Some simple CPU cores can also be obtained for free on the Internet. Even very advanced CPU cores can be obtained through negotiation with integrated circuit manufacturers if they need to be made into real ASICs by chip production. Before chip production, FPGA can also be used to verify whether the circuit structure of the designed complex digital system is correct. To achieve this, we must first clarify a concept: the basic components, macro devices or CPU cores of these digital systems are all described in HDL language, some using structural level description; some using user-defined primitive UDP (i.e. logical truth table) description; some using register transfer level description; some using high-level behavioral description. Regardless of which level of HDL language is used, they all belong to HDL language (either Verilog HDL or VHDL). Since the HDL language for describing digital systems is relatively mature and has been used for a long time, simulation and synthesis tools are already mature, and there is no major difficulty in carrying out design work in this field. The design of SOC can start with a simple digital system, and then carry out the design of digital-analog mixed signal systems on this basis, which can save a lot of investment. The design of electronic chips has become an international industry, and many young people are enthusiastic about participating in this challenging industry. On the basis of improving the quality of engineering education, my country has great advantages in brain-intensive knowledge industries. Most of our college students majoring in electronics have good logical thinking ability. The key is that this work needs to be well organized and planned to improve the quality, standardization and reusability of modules at various levels to reduce duplication of work and achieve the goal of improving international competitiveness. To further reduce the burden of modeling, many EDA companies in the United States have recently introduced component libraries for new communication systems. It is reported that these component libraries allow members of the design team to modify the equations of the model to develop various different models, and the development time required is only a small fraction of the original time. All these models are compatible with the new mixed-analog HDL standard. For example, in addition to announcing the new component library, Mentor Graphics recently revealed a language development plan in cooperation with Motorola, which aims to provide a new way for SOC development to stimulate the development of mixed-signal applications in the design fields of various chips (including electromagnetic sensors and RF communication chip design), which can enable engineers to switch from traditional Spice-based analog design methods to simpler top-down design methods with a system style. Using this method, mixed-signal component models expressed in different behavioral description languages can be put into a design to verify the entire design. Many high-tech companies have not only introduced various component libraries with variable parameters, but are also working hard to develop design simulation tools for analog and digital mixed SOCs. The following lists the latest technical developments of some foreign companies in the field of mixed-analog SOCs: 1? Cadence has combined the emerging Verilog-AMS standard with different simulation algorithms and analysis tools and the traditional Spice netlist representation method, so that such a simulator (i.e. Spectre) can be applied at different levels of the design process. Cadence also provides Verilog-A language debugging and error detection tools and graphical user interfaces. 2? Apteq Design Systems also provides users with some model examples when providing their Verilog-A products. Apteq also provides a distinctive Verilog-A plug-in that can add OVI-compatible Verilog-A HDL function blocks to the existing Spice simulation environment. This product provides a unified high-performance analog HDL interface through a unique connector solution, enabling it to connect to any Spice type simulator, ensuring portable HDL compilation, and correctly evaluating the performance of different types of simulators. The working mechanism of the Verilog-A plug-in is to first convert the simulated behavior program into an intermediate expression through compilation, which can be used by the Spice hardware description language socket and other Spice components for common tasks (such as instance abstraction, parameter setting, loading and evaluation). The plug-in can provide debugging, optimization and dissection of simulated behavior coding. And if simulation, full chip verification and testing are required, the Verilog-A plug-in also has an optional secondary compilation mode, which can provide high-speed, native-code simulation performance. 3? Transcendent Design Technology provides Verilog-A/AMS simulation capabilities in its product TransVerSE. The purpose of this product is to simulate complex electromechanical systems. It targets a number of different industrial fields, including the automotive industry, aircraft industry, aerospace industry and consumer electronics industry. TransVerSE supports Verilog-A, the emerging Verilog-AMS language, Spice and its models and subcircuits, as well as models written in C language. In summary , the design of complex SOC is a systematic project that requires talents from many aspects of the organization society. Over the past 10 years, foreign countries have gradually reached the current level through the mutual cooperation and support of many high-tech companies and university research institutions. Due to various reasons, China's electronic high-tech chip design field has relatively little communication with foreign countries, and domestic counterparts have rarely contacted each other, and the level is relatively backward. There is also a lack of experienced and capable teachers in relevant universities. These are the reasons why the gap between us and advanced countries such as the United States has widened. In recent years, due to the popularization of the Internet, the introduction of foreign EDA tools, the free development software provided by many large FPGA manufacturers, the demand for domestic product upgrades, the small and medium-sized design projects gradually transferred from abroad, and the enthusiasm of young university graduates and postgraduates, it is possible for us to catch up in the field of complex digital SOC design in a relatively short period of time.
4. Design of digital SOC-basic tools and methods
Engineers familiar with MCU development know that MCU development requires a development system. The development system is usually based on a PC. Using the software and emulator provided by the development system manufacturer, the assembly written for the MCU can be compiled and debugged, and the compiled machine code can be downloaded to the prototype system for operation and debugging. The design method of digital SOC is very similar to this, the difference is that we often use an MCU core to replace the real MCU when doing simulation. MCU can be a firm core running on a certain FPGA, a hard core of a certain ASIC process, or a synthesizable (or non-synthesizable) soft core (or virtual module) described in HDL language. There is no substantial difference between debugging the assembly running on MCU and the traditional debugging method. The main difference is that the traditional method must load the program code into the prototype system before debugging the hardware and software coordination; while the design environment of the digital SOC allows debugging the coordination of hardware and software completely in the virtual hardware environment. Because in this environment, each specific hardware module is based on the hardware description language, and the compiled machine code is some binary disk files, which can be loaded into the memory variables in the HDL module through the HDL system task. The debugging process can be carried out completely in the HDL simulation environment. If the hardware needs to be modified, it is only necessary to re-edit or modify individual modules. After the debugging is basically completed, the entire hardware system including the MCU core can be loaded into a large-capacity FPGA for hardware and software joint debugging and verification of the actual circuit structure. After such verification, the hardware structure can be determined. If the required batch is relatively large, you can consider wafer production, and the remaining wafer production verification and yield verification can be done by the back-end integrated circuit manufacturer. For designers of MCU embedded systems, it is not difficult to learn the design method of SOC, just change the simulation environment and learn HDL language. When learning HDL language, the author thinks it is better to learn Verilog HDL first: first, it is easy to get started; second, there are many integrated circuit manufacturers who accept Verilog HDL code as back-end chips, and there are many ready-made hard cores, solid cores and soft cores. When learning HDL language, you should pay attention to distinguishing the two different applications of the language: one is to automatically generate circuit structure, and the other is to debug the circuit structure being designed. At present, the subset of HDL language that can automatically generate circuit structure is very small, the syntax phenomenon is very limited, and the format of program modules does not change much, which is relatively easy to master. The syntax phenomenon included in the HDL language for debugging is very wide, and the style of test modules is also diverse. Interested readers who have a certain foundation in C language programming and some basic hardware knowledge can learn it within 2 months through self-study under the guidance of a good book, and can gradually transition from simple to complex SOC design.
5. Introducing a practical SOC design environment
ALTERA recently launched a SOC development tool kit (called Excalibur Development Kits). Because of its comprehensive performance, it is suitable for the development of digital SOCs. The development kit includes various tools and resource software necessary for SOC development, a reconfigurable hardware circuit structure verification platform and user manual. The software resources that can be used include a variety of embedded processor cores for selection, ALTERA series FPGA development tools (called Quartus, which can perform simulation, synthesis, layout and routing of HDL design), and industrial standard C/C++ compilers. The reconfigurable hardware platform can be used to verify whether the design is correct. After the code representing the hardware structure circuit is generated, it can be loaded through a PC and its circuit can be reconfigured. The purpose of verification can be achieved by running the reconfigured circuit. There are many types of CPU cores that can be embedded in the development software package. They are all high-performance RISC structure CPUs, the highest of which is a 64-bit structure, with a maximum running speed of up to 200 MIPS, and are applicable to a wide range of applications. Among them, there is a CPU core developed by ALTERA (called Nios), which is very easy to implement the operation of its circuit structure on ALTERA's APEX series FPGA, and there is no need to pay patent fees. This CPU core is a parameterized soft core. Designers can optimize the CPU core itself according to the needs of the application and add the functions of the peripheral circuits. These tasks are nothing more than writing some new HDL modules or rewriting some parameters in the existing HDL modules, and then compiling them to complete. This CPU core only occupies 2% of the resources of the APEX series FPGA chip. If you need to increase the processing speed, you can use multiple Nios cores for parallel processing. Such a parallel system including peripheral circuits can be fully implemented on an APEX series FPGA of ALTERA. Therefore, the author believes that the design of SOC is not a distant and unattainable thing. We can buy a set of such a system, start with the development of FPGA, and then decide whether to migrate to ASIC according to the market demand. Since our design is described by a synthesizable HDL module, it is relatively easy to migrate. All you need to do is to use ASIC synthesis tools (such as Synposys or Ambit, etc.) to do synthesis, and then use the relevant peripheral models to do gate-level structure simulation verification with routing delay. If there is no problem, it can be handed over to the integrated circuit manufacturer for chip testing.
Conclusion
I hope that everyone can master the design method of HDL language as soon as possible based on their existing work, and use relatively cheap high-level FPGA development tools to start the development of SOC. We will strive to make great progress in the design of basic chips in the next five years, so that the development of the electronics industry will have a better foundation. Let us work together to achieve this common goal.
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
