1. Background
This article mainly uses ADI's ADF4107 frequency synthesizer chip to design a C-band local oscillator, which is mainly used for Ku-band satellite down-conversion. The customer did not say much about the specific application details, which I understand because this is also a project of a certain research institute. It only said that the frequency range is 4.8-5.2GHz. This product is currently in use. Let's share how to design this frequency synthesizer.
2. Product Introduction
First, let us briefly describe the principle of the phase-locked frequency synthesizer.
The phase-locked loop is a phase negative feedback system that uses phase-locked technology to generate the required frequency. It is the second generation of frequency synthesis technology. The early indirect frequency synthesizer used an analog phase-locked loop. When it outputs a higher frequency, it requires a large number of mixers and frequency dividers, as well as bandpass filters. Therefore, its shortcomings are obvious and difficult to make up for. The digital phase-locked loop makes up for these shortcomings of the analog phase-locked loop. The digital phase-locked loop consists of several parts such as a phase detector, a frequency divider, a loop filter, and a voltage-controlled oscillator.
The following is a block diagram of a single-loop integer frequency division phase-locked loop. As shown in Figure 1:
Figure 1 Block diagram of single-loop integer frequency division phase-locked loop
It is easy to see from the figure above that the digital phase-locked loop is mainly composed of a phase detector, a loop filter, a voltage-controlled oscillator and a frequency divider. Modern phase-locked loop chips include a charge pump circuit.
Basic principle: The reference crystal oscillator generates a stable reference frequency, which is then divided by the reference divider R. The divided frequency is the phase detector frequency, which serves as an input signal of the phase detector. The phase detector detects the phase difference between the phase detector frequency and the output frequency of the N divider, and outputs a DC current whose average value is proportional to the phase difference. The pulse current output by the phase detector is filtered and integrated to generate a regulating voltage, which drives an external voltage-controlled oscillator to increase or decrease the output frequency until the average output of the phase detector is zero.
The loop filter is a low-pass filter, which comes in two forms;
1. Passive filters are usually composed of resistors and capacitors.
2. Active filter, usually composed of resistors, capacitors and operational amplifiers.
For detailed design, please refer to phase-locked loop books or other literature. I will not go into details here.
Next, design how to implement a C-band frequency synthesizer, the technical indicators of the frequency synthesizer are as follows;
Frequency range: 4.8GHz---5.2GHz
Frequency step: 1MHz
Spurious suppression: ≤-50dbc
Harmonic suppression: ≤-50dbc
Phase noise: ≤-60dbc/Hz@ 1kHz
≤-75dbc/Hz@ 10kHz
≤-110dbc/Hz@ 100kHz
Output power: ≥10dbm
Working temperature: -40~+50℃
3. Design
1. Phase detector selection: within the frequency range used, the normalized noise floor should be as low as possible, and it should have good spurious indicators. There are many types of phase detectors on the market, such as Analog Devices, Hittite, Max, Ti, etc. The output frequency of this product is in the C band. After comparison, it was decided to use ADI's ADF4107 chip, which has a bandwidth of up to 7GHz. A low-noise digital phase detector is integrated inside the chip, as well as a precision charge pump, programmable pre-distributor, a front dual-mode divider, and a programmable counter. It is powered by a single power supply with a supply voltage of 2.7~3.3V, which can be met by many step-down chips on the market. It uses a 3-wire serial port control, which is very convenient to use. As shown in Figure 2. Internal schematic diagram of the ADF4107 chip:
Figure 2 ADF4107 internal schematic
2. VCO selection: The voltage-controlled oscillator chip selected for this product is: V950ME08-LF from Z~communications, and its technical parameters are as follows;
1. Output frequency: 4450----5350MHz
2. Working voltage: +5V
3. Working current: 30mA
4. Output power: 0dbm
5. Voltage control sensitivity: 120MHz/V
6. Voltage control range: 0~9.5V
7. Phase noise: -87dbc/Hz@10KHz
The following is the voltage-controlled frequency curve provided by the manufacturer, as shown in Figure 3:
Figure 3 Voltage control curve of voltage controlled oscillator
3. Loop filter
The loop filter plays a vital role in the phase-locked loop circuit, and it is closely related to the various indicators of the phase-locked loop. Adjusting the component parameters of the loop filter can effectively improve the phase noise and spurious indicators of the phase-locked loop. Since the maximum charge pump of the ADF4107 is around 5V, according to the VCO voltage-frequency curve, when the output frequency is 5.2GHz, the voltage control voltage is above 7V, so an active loop filter is required.
When designing the loop filter, you can use the simulation software ADISimPLL provided by ADI to design it, as shown in Figure 4:
Figure 4 ADISimPLL software simulation circuit diagram
The loop filter parameters simulated by ADISimPLL software are only an initial value. In the actual circuit, the phase-locked loop made according to this initial value is likely to fail to lock or fail to meet the system technical indicators. The loop parameters must be repeatedly adjusted to achieve the best.
The figure below is the simulated phase noise, as shown in Figure 5;
Figure 5 Simulated phase noise curve
Figure 5 shows the simulated phase noise. The center frequency is 4.9GHz and the phase noise is -80dbc/Hz@1kHz.
Since the technical requirement is that the frequency synthesizer output power is greater than 10dbm, the VCO output is only 0dbm, and after power distribution, the final output is only -3dbm, so a boost amplifier is added to the VCO output port, and the amplifier uses ADI's ADL5545, as shown in Figure 6;
Figure 6 ADL5545 chip introduction
As shown in Figure 6, the bandwidth of the amplifier covers 30MHz~6GHz, and the input and output ports are matched to 50 ohms, which also saves the trouble of external adjustment and matching, saving valuable time for product design. P1db: +18dbm@900MHz, even in the 5GHz frequency band, P1db is above 10dbm. The circuit is simple, powered by a single +5V power supply, and is well compatible with system design.
The specific parameters are shown in Figure 7;
Figure 7 ADL5545 chip test diagram
As shown in Figure 7, the frequency range given is 4GHz~6GHz, and the designed frequency synthesizer falls within this frequency range. As shown in the figure: at 4.8GHz~5.2GHz, the amplifier gain is about 17db, P1db is above 10dbm, and OIP3 is greater than 30dbm, which proves that the linearity of the amplifier is good, so this amplifier is used for design.
4. Circuit Design
As shown in Figure 8; the C-band frequency synthesizer circuit designed for this project. The frequency synthesizer uses the ADF4107 chip, and the peripheral circuit refers to the technical manual. The reference crystal oscillator uses the KDS temperature-compensated crystal oscillator. If higher precision is required, a constant temperature crystal oscillator can be used. The VCO uses the V950ME08-LF from Z~communications, which has been introduced before and will not be described here. The loop filter uses active filtering and is designed with the AD820 operational amplifier of ADI. You can refer to the ADISimPLL software for design. Finally, the power amplifier uses the ADL5545 of ADI for amplification. When connected together, it is a complete frequency synthesizer circuit. I did not give the microcontroller circuit (I used the STC microcontroller), and it can be controlled by different types of microcontrollers. It has a 3-wire serial port, which is very simple.
Figure 8 Frequency synthesizer circuit diagram
Here we mainly want to say that π attenuation is added between the VCO output and the amplifier, which mainly adjusts the gain of the RF output to ensure the linearity of ADL5545.
5. PCB design + structural design
The PCB is designed with RO4350B high-frequency board, with a dielectric constant of 3.66 and a board thickness of0.762mm, as shown in Figure 9;
Figure 9 Frequency synthesizer PCB
The shell is made of 6061 aluminum alloy, CNC processed, and the shielding box has internal partitions to prevent crosstalk.
Shielding box size: length 800mm x width 55mm x height23mm, as shown in Figure 10;
Figure 10: Frequency synthesizer
6. Actual Test
The phase noise test using R&S spectrum analyzer is shown in Figure 11;
Figure 11 Phase noise test diagram
As shown in Figure 11, the center frequency is 4.9GHz, and the test phase noise is: -111dbc/Hz@100k
The frequency synthesizer phase noise delivered to the customer and tested by the customer himself is shown in Figure 12;
Figure 12 Customer test phase noise
Center frequency 4.9GHz, test phase noise: -65.9dbc/Hz@1k
-77.7dbc/Hz@10k
-110dbc/Hz@100k
Through the above test comparison, customer needs are basically met. The indicators of this source can be improved, but the loop filter needs to be adjusted repeatedly, which takes a lot of time.
7. Summarize the problems encountered in debugging
In this design, the biggest workload is debugging the loop filter, because the loop filter determines the quality of the frequency synthesizer, or it can be said that the loop filter is the core of the frequency synthesizer. Therefore, it needs to be adjusted repeatedly to achieve the best.
The following is analyzed according to the actual circuit, as shown in Figure 13;
Figure 13 Loop filter circuit diagram
1. Adjustment of loop bandwidth
In the circuit of Figure 13, C1 and C3 have the greatest impact on the loop bandwidth. As the capacitance increases, the bandwidth becomes narrower, and as the capacitance decreases, the bandwidth becomes wider.
2. Adjustment of insertion loss within the band
In the circuit of Figure 13 , R1 has the greatest impact on the in-band insertion loss. As the resistance value increases, the insertion loss increases, and as the resistance value decreases, the insertion loss decreases.
3. Adjustment of intra-band fluctuations
In the circuit of Figure 13, R3 and C2 have a greater impact on the in-band fluctuation. Increasing the resistance will reduce the in-band fluctuation. However, the resistance and capacitance will also affect the loop bandwidth and insertion loss, so they must be adjusted together.
There is another important question
During the design process, MAX232 was added to the circuit as a communication device between the host computer and the frequency synthesizer. During debugging, it was found that the MAX232 oscillation generated a switching frequency, which was then modulated to both ends of the carrier. At first, it was thought to be a leakage of the phase detector, and the loop was adjusted. After repeated adjustments, there was no improvement. Later, it was discovered that it was the oscillation of MAX232, so the MAX232 was removed from the PCB board, and the problem was finally solved.
Recommendation: It is best not to use a DC-DC power supply to directly power the frequency synthesizer or VCO inside the frequency synthesizer. Even if efficiency is sacrificed, a linear power supply should be used. Unless the switching frequency can be completely suppressed, it will be modulated to both ends of the carrier and will be difficult to remove.
The above is the whole process of how to design a frequency synthesizer. As for some detailed theoretical issues, you still need to refer to books and literature. The most important thing is the debugging of the loop filter, and I have shared the method. Debugging depends on basic skills.
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