Do the seemingly redundant but actually useless gold-plated leads of gold fingers have any impact on high-speed signals?

yvonneGan

Do the seemingly redundant but actually useless gold-plated leads of gold fingers have any impact on high-speed signals? [Copy link]

First of all, let me briefly explain why Chris wrote this article, which should have been about process knowledge from Dong Ge! This article was born out of a chance conversation. Chris was filling water at the water dispenser that day, and happened to see Xiao Ma Ge, a colleague from the isolation packaging department, coming over. He had just finished a meeting with a friendly board factory. It was probably about the board factory's ability to discuss the process of lead residue after gold plating when making gold finger boards. So he casually mentioned it to Chris and said, "I don't know if the lead residue of 5mil to 15mil has any impact on the SI performance of the signal!" Indeed, we have seen many gold finger boards with lead residue after processing, but we have never quantified its impact before!

So Chris promised Xiao Ma Ge without hesitation that he would take time to study the lead residue to see what effect the lead has on the signal. Of course, Chris still had an idea in his mind and roughly knew how high the signal rate would be to have an impact. 1G and 2G signals are of course not a big problem, compared to the length of the lead, which is about 10mil. So Chris put the object of research on the higher-speed PCIE signal. There are two reasons. One is that the signal rate of PCIE reaches 16Gbps to 32Gbps (4.0 and 5.0 protocols), and the other is that the gold fingers we mentioned are basically used for the transmission of PCIE signals. Of course, another large proportion is DDR memory sticks. So it is no surprise that the object of our research is locked on the PCIE signal.

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What, you don’t know much about the gold-plating process of gold fingers or even why gold-plating is needed? In this case, you may need to read Dong Ge’s article first or harass him directly. Chris will not elaborate on the process issues on this occasion, lest the article becomes too long and the article stops at a critical moment. We can only wait until next week to get a conclusion! According to the further communication between Chris and the packaging brother Ma, we know that the process capability of a certain board factory for gold fingers is as follows:

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First, Xiao Ma introduced the two processing capabilities of this board factory for gold finger processing. One is to leave the lead wire at about 5mil, and the other is to leave the lead wire at a maximum of 15mil through conventional mechanical forming. The lead wire process within 5mil is achieved through dry film etching, as shown in the figure below.

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The 15mil mechanical forming method really relies entirely on physical addition, which is achieved through the chamfering method!

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Again, if you are interested in the process implementation itself, go find Brother Dong and ask for clarification. The following is the time of Chris's high-speed simulation verification! Of course, it was mentioned above that this board factory is making gold fingers for transmitting PCIE5.0, so Chris directly studied 5.0. Before long, Chris dug out a model built for a PCIE5.0 gold finger project he had done before, so we will study the impact of three cases on PCIE5.0 signals under the ideal situation of no lead residue, 5mil lead residue, and the worst 15mil lead residue. The modeling is shown below:

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Yes, we simulated three cases with different lead states, so what we want to do next is to verify the performance of these three gold finger models when they are inserted into the PCIE slot. Yes, it is the model below!

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Then let's first look at the comparison of the TDR impedance of the two models after being inserted into the slot in the ideal state without lead residue and with 5mil lead residue, as shown below:

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It feels okay, the impedance is only reduced by about 1 ohm, which is basically no effect! It seems that if the lead residue can be kept within 5mil, the impact on signal quality is actually controllable!

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What if there is 15mil of lead remaining? Let’s continue reading. Similarly, we simulate the 15mil case3 model, and then put the TDR impedance results together for comparison. Isn’t the impact here?

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Sure enough, the 15mil lead residue has a much greater impact, and the impedance is 4-5 ohms lower than when there is no lead residue, which is a considerable amount of magnitude. At this time, if we look at another frequency domain indicator, return loss, we can also clearly see the deterioration of the 15mil lead residue.

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To summarize briefly, it seems that the gold-plated lead residue process of the gold finger is also "foresighted". The lead residue within 5mil, which has a high process difficulty, does not have much impact on the signal quality, but the lead residue within 15mil, which has a slightly lower process difficulty, has a really significant impact. For us SI, we need to take this part of the impact into consideration in the design, and evaluate whether the signal margin is sufficient on this basis!