[Domestic FPGA Evaluation] Anlu (Model SF1S60CG121I) 06 Using SF1 hard core and UART driver
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This post was last edited by EPTmachine on 2023-4-22 21:47
1.1 Use IP Generator to generate RISC-V hard core and PLL core
Create a project and select the device as SF160CG121I.
Click Tools->IP Generator, select Create an IP core, and generate the RISC-V core SF1_MCU and the PLL core sys_pll.
1.2 Design GPIO interface circuit
When creating the SF1_MCU IP, three GPIO outputs were selected, and three groups of GPIO-related ports will appear on the schematic diagram on the left.
Each group of ports consists of gpiox_in, gpiox_out, gpiox_dir (x=0,1,2,3….n). A control circuit needs to be added to connect to the physical port of FPGA. In this control circuit, gpio_dir controls whether the physical port is connected to gpio0_in or gpio0_out. The specific code is as follows:
module gpio_controller(
output wire O_gpio_in,
input wire I_gpio_dir,//1'b0:input ,1'b1:output
input wire I_gpio_out,
inout wire IO_gpio
);
assign IO_gpio = I_gpio_dir?I_gpio_out:1'bz;
assign O_gpio_in=IO_gpio;
endmodule
1.3 Design and use of SOC module
Combine the above configured RISC-V IP core and GPIO interface circuit module to form a SOC module that can be called externally. The specific code is as follows:
module SF1_SOC(
input wire I_clk,
input wire I_rst,
input wire I_timer_clk,
input wire I_jtag_tck,
output wire O_jtag_tdo,
input wire I_jtag_tms,
input wire I_jtag_tdi,
input wire I_uart_rx,
output wire O_uart_tx,
inout wire IO_gpio_0,
inout wire IO_gpio_1,
inout wire IO_gpio_2
);
wire S_gpio0_out;
wire S_gpio0_dir;
wire S_gpio0_in;
wire S_gpio1_out;
wire S_gpio1_dir;
wire S_gpio1_in;
wire S_gpio2_out;
wire S_gpio2_dir;
wire S_gpio2_in;
//gpio_controller instances
gpio_controller u0_gpio_controller(
.O_gpio_in(S_gpio0_in),
.I_gpio_dir(S_gpio0_dir),
.I_gpio_out(S_gpio0_in),
.IO_gpio(IO_gpio_0)
);
gpio_controller u1_gpio_controller(
.O_gpio_in(S_gpio1_in),
.I_gpio_dir(S_gpio1_dir),
.I_gpio_out(S_gpio1_in),
.IO_gpio(IO_gpio_1)
);
gpio_controller u2_gpio_controller(
.O_gpio_in(S_gpio2_in),
.I_gpio_dir(S_gpio2_dir),
.I_gpio_out(S_gpio2_in),
.IO_gpio(IO_gpio_2)
);
//SF1_MCU
SF1_MCU u_SF1_MCU(
.core_clk(I_clk),
.timer_clk(I_timer_clk),
.core_reset(I_rst),
.jtag_tck(I_jtag_tck),
.jtag_tdo(O_jtag_tdo),
.jtag_tms(I_jtag_tms),
.jtag_tdi(I_jtag_tdi),
.soft_ip_apbm_en(1'b0),
.qspi0cfg1_mode(1'b1),
.qspi0cfg2_mode(1'b1),
.uart_tx(O_uart_tx),
.uart_rx(I_uart_rx),
.gpio0_out(S_gpio0_out),
.gpio0_dir(S_gpio0_dir),
.gpio0_in(S_gpio0_in),
.gpio1_out(S_gpio1_out),
.gpio1_dir(S_gpio1_dir),
.gpio1_in(S_gpio1_in),
.gpio2_out(S_gpio2_out),
.gpio2_dir(S_gpio2_dir),
.gpio2_in(S_gpio2_in),
// .mtip(),
// .apb_clk(),
// .apb_paddr(),
// .apb_pwrite(),
// .apb_penable(),
// .apb_pprot(),
// .apb_pstrobe(),
// .apb_psel(),
// .apb_pwdata(),
// .apb_prdata(),
// .apb_pready(),
// .apb_pslverr(),
.nmi(),
.clic_irq(),
.sysrstreq(),
.apb_clk_down(),
.apb_paddr_down(),
.apb_penable_down(),
.apb_pprot_down(),
.apb_prdata_down(),
.apb_pready_down(),
.apb_pslverr_down(),
.apb_pstrobe_down(),
.apb_pwdata_down(),
.apb_pwrite_down(),
.apb_psel0_down(),
.apb_psel1_down(),
.apb_psel2_down()
);
endmodule
Called in TOP module, SOC module and PLL module
Add pin constraints and sort out the IO port connections used by viewing the hardware schematic.
| TOP port |
FPGA Port |
Peripherals |
| I_clk_25m |
D7 |
25M passive crystal oscillator |
| I_rst_n |
H3 |
Key K0 |
| I_jtag_tck |
C7 |
JTAG TCK pin |
| O_jtag_tdo |
C6 |
JTAG TDO pin |
| I_jtag_tms |
D6 |
JTAG TMS pin |
| I_jtag_tdi |
D5 |
JTAG TDI pin |
| O_led0 |
J4 |
LED0 |
| O_led1 |
H5 |
LED1 |
| O_led2 |
J5 |
LED2 |
| I_uart_rx |
E4 |
SF1_UART_RX |
| O_uart_tx |
A4 |
SF1_UART_TX |
After adding the IO constraints and timing constraints, you can generate the bitstream file and prepare for the subsequent download.
2.RISC-V Programming
The above process completes the implementation of the RISC-V hard core. Next, you need to write a program that runs on the RISC-V processor.
2.1 Development Environment Preparation
The RISC-V hard core program on SF1 is carried out in the Future Dynasty (FD) integrated development environment. The development tool can directly decompress the compressed package to the hard disk. Be careful not to have Chinese in the path, otherwise there will be garbled characters, the compiler cannot be executed, and other problems.
2.2 Create a project
Select Project in File->New and create the gpio_demo project according to the process shown in the figure below.
2.2 Download Project
After the creation is completed, due to the bug in the baud rate driver of the serial port driver, the driver needs to be modified. The modification location is located at
After the modification, UART can be used normally. After compiling the project, check the generated binary files in the Debug folder of the project. Return to the TD software and click the Download button in the toolbar. Select the FPGA bitstream file and the Hex file of the RISC-V project on the page, and select PROGRAM RISCV IMG as the download method. When downloading, remember to click the bitstream file in the file list so that there will be no error when downloading.
2.3 Running the Demo
09演示
Engineering accessories
| 
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变色卡
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