Serial to Parallel Solution

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Serial to Parallel Solution [Copy link]

 

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Hello everyone, I recently have a design expectation to use multiple serial-to-parallel data chips to drive multiple IO ports at the same time. The truth table of the selected chip is as follows, and the data sheet is as follows.

Based on this truth table, discuss whether the following functions can be realized.

1. Under the premise of maintaining the current state, serial data is input. After multiple clock cycles, for example, 3 chips are connected in series, 24 bits of data are written, and each chip corresponds to 8 data, which are stored in the storage register.

2. Control data output and repeat the previous step after a while.

吾妻思萌

You can use the high eight bits and low eight bits to manipulate the memory.

呜呼哀哉

Azuma Simeng posted on 2023-1-31 16:07 The memory can be manipulated by the high eight bits and the low eight bits~

There is only one DS for input data, which is recognized by the clock edge. This is to save wires. Parallel direct latching can do what you said.

chunyang

Of course, 595 is the most commonly used serial-to-parallel chip.

chunyang

Alas, published on 2023-1-31 16:16 The input data is just a DS, which is recognized by the clock edge. This is to save wires. Parallel direct latching can go as you said.

595 requires 3 IOs for control, serial output, clock and latch control.

maychang

74LVC595 is an 8-bit serial-input-parallel-output register chip. Three such chips can be cascaded to achieve 24-bit serial data input and 24-bit parallel data output.

maychang

However, I don't understand what "the current state is maintained" means. In addition, I don't know whether you want the microcontroller to output serial signals and then output them in parallel to devices such as 8-bit digital tubes, or other devices to output serial data to 595 and then the microcontroller reads the parallel data.

呜呼哀哉

maychang posted on 2023-1-31 16:27 However, I don't understand what "under the premise of maintaining the current state" means. In addition, I don't know if you want the microcontroller to output serial...

For example, I need to control 24 indicator lights. All lights are in the state of 101010.... If I want them to be in the state of 010101..., how can I ensure that the lights do not flash when 010101 is input on the data line? I really don't understand this truth table. Is it because the clock speed is so high that the lights cannot be seen even if they flash?

maychang

Alas, published on 2023-1-31 16:31 For example, I need to control 24 indicator lights, all of which are in the 101010... state. If I want them to become 010101... state, how can I ensure that the data line is 0...

Please wait. I just replaced my desktop computer with a new one, and the files in the original hard disk have not been moved to the new computer. I need to go to the original computer to look at the 595 datasheet.

maychang

Alas, published on 2023-1-31 16:31 For example, I need to control 24 indicator lights, all of which are in the 101010... state. If I want them to become 010101... state, how can I ensure that the data line is 0...

Just from memory, the 595 chip can output all the parallel data synchronously after the serial transmission is completed, that is, 24 bits of parallel data can be output synchronously, so of course the indicator lights will not flash. However, if the serial data transmission is fast enough, the human eye cannot see it.

定云止水

Yes, the 4th line in the function table is to move the data while keeping the parallel output unchanged, and the 5th line is to move the current serial to the corresponding position and output the data in parallel.

wangerxian

It seems to be possible. When we took analog classes before, we used this logic to drive digital tubes.

maychang

Alas, published on 2023-1-31 16:31 For example, I need to control 24 indicator lights, all of which are in the 101010... state. If I want them to become 010101... state, how can I ensure that the data line is 0...

I checked and my memory is correct. The 595 can output 24 bits of parallel data simultaneously after the 24 bits of serial data are transmitted .

呜呼哀哉

maychang posted on 2023-1-31 17:53 I checked and my memory is correct. 595 can output 24-bit parallel data at the same time after 24-bit serial data transmission is completed.

This situation cannot be seen in the truth table. The output is maintained, and some conditions of the shift data Q7S have DS=1. This is too incomprehensible.

chunyang

595 has output latch. When there is no latch signal, the output will not change and remain in the current state. The output will only be updated after the latch signal occurs.

maychang

Alas, published on 2023-1-31 18:26 This situation is not seen in the truth table. The output is maintained, and some conditions of the shift data Q7S have DS=1. This is too incomprehensible.

It is clear from the functional block diagram and logic block diagram that when the OE pin is low, the contents of the shift register will be sent to the 8 pins Q0~Q7.

maychang

Alas, published on 2023-1-31 18:26 This situation is not seen in the truth table. The output is maintained, and some conditions of the shift data Q7S have DS=1. This is too incomprehensible.

Q7S is the shift output and should be connected to the input of the next 595.

From the logic block diagram, the 8 output terminals (8 Q terminals) of the shift register are connected to the input terminals (8 D terminals) of the 8-bit latch. When the SRCP pin is activated (it may be the rising edge or the falling edge, I did not check it carefully. I used it before, but now I forget it), the 8 Q terminal data of the shift register is entered into the 8-bit latch. If the OE terminal allows output, the 8-bit latch output will appear on the pin.

呜呼哀哉

maychang posted on 2023-2-1 08:19 Q7S is the shift output and should be connected to the input of the next 595. From the logic block diagram, the 8 outputs (8 Q terminals) of the shift register are connected to the 8-bit...

From the truth table in the post, we can see that OE cannot be controlled and must always be low. When it is high, the output becomes high impedance. So is there something wrong with this truth table? Or is it downloaded from the official website?

maychang

Alas, published on 2023-2-1 09:02 From the truth table of the post, we can see that OE cannot be controlled and must always be low. When it is high, the output becomes high impedance, so does this truth table have...

This truth table is probably fine. The OE terminal controls the 8-bit output pin to be in high impedance state or output high or low level. If high impedance state is not required, the OE terminal can be grounded (not controlled by the microcontroller). The microcontroller needs to control the three lines DS, SHCP, and STCP. Among them, DS is the serial signal, SHCP is the serial clock (shift signal), and STCP is the signal that puts the contents of the shift register into the latch.

maychang

Alas, published on 2023-1-31 18:26 This situation is not seen in the truth table. The output is maintained, and some conditions of the shift data Q7S have DS=1. This is too incomprehensible.

The fifth row of the truth table describes the function of the STCP pin. When the pin rises, the contents of the shift register are entered into the storage register.