[Domestic FPGA Zhengdian Atom DFPGL22G development board] 3. AD7606 driver writing

Jimmy_Arareb

[Domestic FPGA Zhengdian Atom DFPGL22G development board] 3. AD7606 driver writing [Copy link]

 

# III. AD7606 driver writing [TOC] ## 1. AD7606 driver AD7606 is a 4/6/8 channel synchronous sampling, 200kSPS, 16-bit, $\pm$5, $\pm$15V bipolar input ADC chip produced by ADI. ### The chip timing refers to the data sheet, using read-after-conversion, parallel port mode. The chip timing is as follows: <ignore_js_op> <img style="cursor:pointer;" id="aimg_671465" aid="671465" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002559wn3y9mnaua89zalw.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002559wn3y9mnaua89zalw.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671465_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-13-16-50-20.png</strong> <em class="xg1">(24.58 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671465" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671465&handlekey=savephoto_671465">save to album</a> </p> <p class="xg1 y">2023-1-14 00:25 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op> <ignore_js_op> <img style="cursor:pointer;" id="aimg_671466" aid="671466" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002559c3ch1qvsbcshb8ra.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002559c3ch1qvsbcshb8ra.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671466_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-13-16-50-57.png</strong> <em class="xg1">(32.25 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671466" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671466&handlekey=savephoto_671466">save to album</a> </p> <p class="xg1 y">2023-1-14 00:25 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op> Note that after power-on, you need to pull up `RESET` to reset the chip, otherwise the chip will work abnormally. Pull down the `CONVST A/B` pin when starting the conversion, and wait for `BUSY` to be pulled low before the conversion is completed. Note that the maximum interval from the start of the conversion to the pull-up of `BUSY` is 45ns, and a separate state needs to be set for processing, otherwise false triggering may occur. After the conversion is completed, pull down `CS` first and then input the clock `RD`. After the reading is completed, pull up `CS` again, and a sampling cycle is completed. Note that the data is updated on the falling edge of `RD` and read on the rising edge. ### The program is written using a state machine to control the reading. It enters the `RESET` state when powered on and reset, and resets the AD7606 first. After the reset is completed, it enters the `IDLE` state and waits for the data acquisition start flag to be input. After the acquisition starts, it enters the `WAIT_1` state. After the timing is completed, it enters the `WAIT_BUSY` state and waits for the conversion to be completed. After `BUSY` is pulled low, it enters the `READ_CH1` to `READ_CH4` states in sequence. After the reading is completed, it enters the `READ_STOP` state. After the read completion signal is sent, it returns to the `IDLE` state and waits for the next trigger. ```verilog `timescale 1ns / 1ps module ad7606_4 ( input clk, input rst, input [15:0] data_in, //ad7606 channel a input parallel read data input ad_busy, //ad7606 input busy signal input capture_flag, //external input start data acquisition flag output reg ad_cs, //read ad7606 enable signal output reg ad_rd, //read ad7606 clock signal output reg ad_convstab, //ad7606 start conversion signal, low level valid output reg ad_reset, //ad7606 reset signal output reg [15:0] data_ch1, output reg [15:0] data_ch2, output reg [15:0] data_ch3, output reg [15:0] data_ch4, output wire capture_over ); localparam RESET = 10'b0_000_000_001; localparam IDLE = 10'b0_000_000_010; localparam AD_CONV = 10'b0_000_000_100; localparam WAIT_1 = 10'b0_000_001_000; localparam WAIT_BUSY = 10'b0_000_010_0 00; localparam READ_CH1 = 10'b0_000_100_000; localparam READ_CH2 = 10'b0_001_000_000; localparam READ_CH3 = 10'b0_010_000_000; localparam READ_CH4 = 10'b0_100_000_000; localparam READ_STOP = 10'b1_000_000_000; localparam RESET_TIME = 5; //reset high level durationlocalparam CONV_TIME = 5; //AD_CONV state duration is equivalent to conversion signal low level durationlocalparam WAIT_TIME = 5; //WAIT_1 state durationlocalparam FIV_CLK = 2; reg [ 9:0] state; reg [ 5:0] cnt; //In data reading state, it indicates the frequency division coefficientreg [2 : 0] over; always @(posedge clk) if (!rst) cnt <= 'd0; else if (state == RESET) if (cnt == RESET_TIME) cnt <= 'd0; else cnt <= cnt + 1; else if (state == AD_CONV) if (cnt == CONV_TIME) cnt <= 'd0; else cnt <= cnt + 1; else if (state == WAIT_1) if (cnt == WAIT_TIME) cnt <= 'd0; else cnt <= cnt + 1; else if (state == WAIT_BUSY) if (ad_busy == 1'b0) cnt <= 'd0; else cnt <= cnt; else if (state == READ_CH1 || state == READ_CH2 || state == READ_CH3 || state == READ_CH4) if (cnt == ( 2 * FIV_CLK - 1)) cnt <= 'd0; else cnt <= cnt + 1; // verilog_format: off // else statement auto format error always @(posedge clk) if (!rst) state <= RESET; else begin case (state) RESET:if (cnt == RESET_TIME) state <= IDLE; else state <= RESET; IDLE: if (capture_flag == 1'b1) state <= AD_CONV; else state <= IDLE; AD_CONV: if (cnt == CONV_TIME) state <= WAIT_1; else state <= AD_CONV; WAIT_1: if (cnt == WAIT_TIME) state <= WAIT_BUSY; else state <= WAIT_1; WAIT_BUSY: if (ad_busy == 1'b0) state <= READ_CH1; else state <= WAIT_BUSY; READ_CH1: if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH2; else state <= READ_CH1; READ_CH2: if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH3; else state <= READ_CH2; READ_CH3: if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH4; else state <= READ_CH3; READ_CH4: if (cnt == (2 * FIV_CLK - 1)) state <= READ_STOP; else state <= READ_CH4; READ_STOP: state <= IDLE; default: state <= IDLE; endcase end // verilog_format: on //Output signal always @(posedge clk) if (!rst) ad_convstab <= 1'b1; else if ( state == AD_CONV) ad_convstab <= 1'b0; else ad_convstab <= 1'b1; always @(posedge clk) if (!rst) ad_cs <= 1'b1; else if (state == WAIT_BUSY && ad_busy == 1 'b0) ad_cs <= 1'b0; else if (state == READ_STOP) ad_cs <= 1'b1; else ad_cs <= ad_cs; always @(posedge clk) if (!rst) ad_rd <= 1'b1; else if (state = = READ_CH1 || state == READ_CH2 || state == READ_CH3 || state == READ_CH4) if (cnt == (FIV_CLK - 1)) ad_rd <= 1'b0; else if (cnt == 2 * FIV_CLK - 1 ) ad_rd <= 1'b1; else ad_rd <= ad_rd; else ad_rd <= 1'b1; //ad7606 reset always @(posedge clk) begin if (!rst) ad_reset <= 1'd1; else begin if (state == RESET) ad_reset <= 1'd1; else ad_reset <= 1'd0; end end //Store the collected data in data_ch1-data_ch4 always @(posedge clk) if (!rst) begin data_ch1 <= 16'd0; data_ch2 <= 16'd0; data_ch3 <= 16'd0; data_ch4 <= 16'd0; end else if (state == READ_CH1 && cnt == (2 * FIV_CLK - 1) ) begin data_ch1 <= data_in; end else if (state == READ_CH2 && cnt == (2 * FIV_CLK - 1)) begin data_ch2 <= data_in; end else if (state == READ_CH3 && cnt == (2 * FIV_CLK - 1)) begin data_ch3 <= data_in; end else if (state == READ_CH4 && cnt == (2 * FIV_CLK - 1)) begin data_ch4 <= data_in; end else begin data_ch1 <= data_ch1; data_ch2 <= data_ch2; data_ch3 <= data_ch3; data_ch4 <= data_ch4; end //After the acquisition of 4 channels is completed, the over signal is processed and over_flag is output assign capture_over = over[2]; always @(posedge clk) if (!rst) over <= 3'd0; else if (state == READ_STOP) begin over[0] <= 1'b1; over[1] <= over[0]; over[2] <= over[1]; end else begin over[ 0] <= 1'b0; over[1] <= over[0]; over[2] <= over[1]; end endmodule ``` ### The simulation test writes the test stimulus according to the timing diagram as follows: `` `verilog `timescale 1ns / 1ps module ad7606_4_tb (); localparam N = 2000; reg clk = 0, rst = 0, ad_busy = 0, capture_flag = 0; reg [15:0] data_sin [N - 1:0]; reg [15:0] data_cos [N - 1:0]; reg [15:0] data_in = 0; reg [1:0] cnt = 0; wire ad_cs, ad_rd, ad_convstab, capture_over, ad_reset; wire [15:0] data_ch1, data_ch2, data_ch3, data_ch4; integer i = 0; initial begin $readmemh("../../matlab/sin.txt", data_sin ); $readmemh("../../matlab/cos.txt", data_cos); #50 rst <= 1; #10000000 $stop; end always begin #10 clk <= ~clk; end always begin #40 capture_flag = 0; #4960 capture_flag = 1; end always @(posedge ad_convstab) begin if (~ad_reset) begin #40 ad_busy = 1; #2000 ad_busy = 0; end else begin ad_busy = 0; end end always @(negedge ad_rd) begin case (cnt) 3'd0: data_in <= data_sin<i>; 3'd1: data_in <= data_cos<i>; 3'd2: data_in <= 0; 3'd3: begin data_in <= 0; if (i == N - 1) begin i < = 0; end else i <= i + 1; end endcase cnt <= cnt + 1; end ad7606_4 u_ad7606_4 ( .clk (clk), .rst (rst), .data_in (data_in), .ad_busy (ad_busy), .capture_flag(capture_flag), .ad_cs (ad_cs), .ad_rd (ad_rd), .ad_convstab (ad_convstab), .ad_reset (ad_reset), .data_ch1 (data_ch1), .data_ch2 (data_ch2), .data_ch3 (data_ch3), .data_ch4 (data_ch4), .capture_over(capture_over) ); endmodule ``` Channels 1/2 are two simulated sin/cos signals, and channel 3/4 inputs are 0. The matlab script for generating the test waveform is as follows: ```matlab N = 2000; n = 1:N; x = fix((2^15 - 1) * sin(2*pi*n/N)); y = fix((2^15 - 1) * cos(2*pi*n/N)); fid1 = fopen('sin.txt','wt'); fid2 = fopen('cos.txt','wt'); for i = 1:N fprintf(fid1,'%s\n',dec2hex(x(i),4)); fprintf(fid2,'%s\n',dec2hex(y(i),4)); end fclose(fid1); fclose(fid2); ``` The simulation waveform is normal and the input signal is read correctly. <ignore_js_op> <img style="cursor:pointer;" id="aimg_671467" aid="671467" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002600mci6cz2bwr2qrb1t.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002600mci6cz2bwr2qrb1t.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671467_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-13-17-16-11.png</strong> <em class="xg1">(74 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671467" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671467&handlekey=savephoto_671467">save to album</a> </p> <p class="xg1 y">2023-1-14 00:25 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op> The timing of a single read is consistent with the data sheet. <ignore_js_op> <img style="cursor:pointer;" id="aimg_671468" aid="671468" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002601qa3tomfxrt1j33j3.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002601qa3tomfxrt1j33j3.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671468_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-13-17-16-21.png</strong> <em class="xg1">(83.47 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671468" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671468&handlekey=savephoto_671468">save to album</a> </p> <p class="xg1 y">2023-1-14 00:26 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op> ## 2. Physical simulation of AD7606 Due to the epidemic, I went home early and did not have the conditions to conduct physical tests on the resolver. At present, I have a ZYNQ that can simulate the input and output of the sensor. The PL part of ZYNQ7010 is used to simulate the timing output sinusoidal signal of AD7606 for testing. ### The timing of program writing is the same as the above introduction, so I will not repeat it here. The code is as follows: ```verilog `timescale 1ns / 1ps module ad7606_sim ( input clk, output reg [15:0] data_out, //ad7606 channel a output parallel read data output reg ad_busy, //ad7606 output busy signal input ad_cs, //read ad7606 enable signal input ad_rd, //read ad7606 clock signal input ad_convstab, //ad7606 start conversion signal, low level valid input ad_reset, //ad7606 reset signal input [15:0] data_ch1, input [15:0] data_ch2, input [15:0] data_ch3, input [15:0] data_ch4 ); localparam RESET = 9'b000_000_001; localparam IDLE = 9'b000_000_010; localparam AD_CONV = 9'b000_000_100; localparam AD_EN = 9'b000_001_000; localparam WRITE_CH1 = 9'b000_010_000; localparam WRITE_CH2 = 9'b000_100_000; localparam WRITE_CH3 = 9'b001_000_000; localparam WRITE_CH4 = 9'b010_000_000; localparam WRITE_STOP = 9'b100_000_000; localparam CONV_TIME = 200; //AD_CONV状态持续时间reg [ 7:0] cnt; reg [ 8:0] state; reg [15:0] data_buf [3:0]; reg [ 1:0] ad_rd_buf; //Read clock cache always @(posedge clk) begin if (ad_reset) begin ad_rd_buf <= 2'b11; end else begin ad_rd_buf <= {ad_rd_buf[0], ad_rd}; end end //Data cache integer i; always @(posedge clk) begin if (ad_reset) begin for (i = 0; i < 4; i = i + 1) begin data_buf<i> <= 16'b0; end end else begin if (state == IDLE) begin data_buf[0] <= data_ch1; data_buf[1] <= data_ch2; data_buf[2] <= data_ch3; data_buf[3] <= data_ch4; end else begin for (i = 0; i < 4; i = i + 1) begin data_buf<i> <= data_buf<i>; end end end end //Counter analog conversion process busy signal always @(posedge clk) begin if (ad_reset) begin cnt <= 8'd0; end else begin case (state) AD_CONV:begin if (cnt == CONV_TIME - 1'b1) begin cnt <= 8'd0; end else begin cnt <= cnt + 1'd1; end end default: begin cnt <= 8'd0; end endcase end end always @ (posedge clk) begin if (ad_reset) begin ad_busy <= 1'b0; end else begin if (state == AD_CONV) begin ad_busy <= 1'b1; end else begin ad_busy <= 1'b0; end end end // Data output always @(posedge clk) begin if (ad_reset) begin data_out <= 16'b0; end else begin case (state) WRITE_CH1: begin if (ad_rd_buf == 2'b10) begin data_out <= data_buf[0]; end else begin data_out <= data_out; end end WRITE_CH2: begin if (ad_rd_buf == 2'b10) begin data_out <= data_buf[1]; end else begin data_out <= data_out; end end WRITE_CH3: begin if (ad_rd_buf == 2'b10) begin data_out <= data_buf[2]; end else begin data_out <= data_out; end end WRITE_CH4: begin if (ad_rd_buf == 2'b10) begin data_out <= data_buf[3]; end else begin data_out <= data_out; end end default: begin data_out <= 16'b0; end endcase end end / /State machine switching always @(posedge clk) begin if (ad_reset) begin state <= RESET; end else begin case (state) RESET: begin state <= IDLE; end IDLE: begin if (~ad_convstab) begin state <= AD_CONV ; end else begin state <= IDLE; end end AD_CONV: begin if (cnt == CONV_TIME - 1'b1) begin state <= AD_EN; end else begin state <= AD_CONV; end end AD_EN:begin if (~ad_cs) begin state <= WRITE_CH1; end else begin state <= AD_EN; end end WRITE_CH1: begin if (ad_rd_buf == 2'b01) begin state <= WRITE_CH2; end else begin state <= WRITE_CH1; end end WRITE_CH2: begin if (ad_rd_buf == 2'b01) begin state <= WRITE_CH3; end else begin state <= WRITE_CH2; end end WRITE_CH3: begin if (ad_rd_buf == 2'b01) begin state <= WRITE_CH4; end else begin state <= WRITE_CH3; end end WRITE_CH4: begin if (ad_rd_buf == 2'b01) begin state <= WRITE_STOP; end else begin state <= WRITE_CH4; end end WRITE_STOP: begin state <= IDLE; end default: state <= IDLE; endcase end end endmodule ``` ZYNQ is developed using Vivado and supports Block Design, which allows easy addition of various Xilinx-provided and customer-written IP cores. Use Block Design to add DDS and Clock Wizard modules After completing the connection, click Generate Block Design to generate the IP core, and then click Create HDL Wrapper to generate the HDL wrapper file for subsequent simulation and synthesis. ### Simulation test Connect the driver and the corresponding ports of the AD7606 simulation module, and write the test stimulus as follows: ```verilog `timescale 1ns / 1ps module top_tb; reg clk_50m = 0, rst = 0, capture_flag = 0; wire ad_busy, ad_cs , ad_rd, ad_convstab, capture_over, ad_reset; wire [15:0] data_ch1, data_ch2, data_ch3, data_ch4, data_out; initial begin #50 rst <= 1; #200000 $stop; end always begin #10 clk_50m <= ~clk_50m; end always begin #40 capture_flag = 0; #4960 capture_flag = 1; end ad7606_4 u_ad7606_4 ( .clk (clk_50m), .rst (rst), .data_in (data_out), .ad_busy (ad_busy), .capture_flag(capture_flag), .ad_cs (ad_cs), .ad_rd (ad_rd), .ad_convstab (ad_convstab), .ad_reset (ad_reset), .data_ch1 (data_ch1), .data_ch2 (data_ch2), .data_ch3 (data_ch3), .data_ch4 (data_ch4), .capture_over(capture_over) ); top_wrapper u_top_wrapper ( .ad_busy_0 (ad_busy), .ad_convstab_0(ad_convstab), .ad_cs_0 (ad_cs), .ad_rd_0 (ad_rd), .ad_reset (ad_reset), .clk_in1 (clk_50m), .data_out_0 (data_out) ); endmodule ``` <ignore_js_op> <img style="cursor:pointer;" id="aimg_671470" aid="671470" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002602fzivqijokao2eapv.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002602fzivqijokao2eapv.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671470_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-13-17-33-01.png</strong> <em class="xg1">(218.83 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671470" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671470&handlekey=savephoto_671470">save to album</a> </p> <p class="xg1 y">2023-1-14 00:26 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op> The simulation waveform is normal. ### Physical test After connecting the two development boards according to the corresponding pins, burn the program separately and use the on-chip logic analyzer to observe the signal. The signal reading is normal. <ignore_js_op> <img style="cursor:pointer;" id="aimg_671471" aid="671471" src="/bbs/static/image/common/none.gif" onclick="zoom(this, this.getAttribute('zoomfile'), 0, 0, '0')" zoomfile="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002602isjbbjc9d4ja6c9s.png" file="//bbs.eeworld.com.cn/data/attachment/forum/202301/14/002602isjbbjc9d4ja6c9s.png" inpost="1" onmouseover="showMenu({'ctrlid':this.id,'pos':'12'})" /> <div class="tip tip_4 aimg_tip" id="aimg_671471_menu" style="position: absolute; display: none" disautofocus="true"> <div class="xs0"> <p><strong>2023-01-14-00-17-58.png</strong> <em class="xg1">(64.8 KB, downloads: 0)</em></p> <p> <a href="javascript:;" class="loginf" >download attach</a> <a href="javascript:;" onclick="showWindow(this.id, this.getAttribute('url'), 'get', 0);" id="savephoto_671471" url="home.php?mod=spacecp&ac=album&op=saveforumphoto&aid=671471&handlekey=savephoto_671471">save to album</a> </p> <p class="xg1 y">2023-1-14 00:26 上传</p> </div> <div class="tip_horn"></div> </div> </ignore_js_op>

lugl4313820

Very cool post, thanks for sharing!

yyliu

Please tell me how to connect the hardware. Is AD7606 a development board resource, or is it driven by the pin header IO pins?

Jimmy_Arareb

yyliu posted on 2023-1-16 09:19 Please tell me how to connect the hardware. Is AD7606 a development board resource, or is it driven by the pin header IO pins?

It is not on the development board, but external. Actually, I want to give Zhengdian Atom some small suggestions. The pin headers on both sides of the development board only have ground wires on the sides, which is easy to cause crosstalk when connecting parallel port peripherals. I hope that the pin headers led out by the future FPGA development board can add a ground wire every few IOs to ensure signal integrity.

In addition, I don't have AD7606 on hand now, so I use another FPGA to simulate the timing of AD7606.