【ST NUCLEO-U575ZI-Q Review】Clock Configuration - Overclocking

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【ST NUCLEO-U575ZI-Q Review】Clock Configuration - Overclocking [Copy link]

Preface

By default, the chip runs at 4MHz internal clock after reset. In order to run at high performance, we need to configure the system clock to run at the maximum clock frequency. This article tests the RCC clock configuration and performs overclocking tests.

process

RCC Module

Reference Manual, "11 Reset and clock control (RCC)"

From the schematic diagram, we can see that there is no HSE crystal soldered on, so we can only use the internal one.

Figure 33. Clock tree You can see the clock tree structure.

We choose HSI RC16 MHz as the system clock.

PLL Settings

See "11.4.6 PLL"

Maximum output clock

The maximum system clock is 160MHz

The PLL input is 4~16 MHz, we choose 16M HSI here

Calculation formula

PLLM: can be set to 1~63

The frequency division value, the input clock of PLL, for example 16MHz/PLLM, is used as the input of VCO. The input of VCO must be 1~16MHz

So we set it to 1 here

PLLN: can be set to 4~512

Frequency multiplication value, VCO input x PLLN is VCO output,

The maximum output value of VCO corresponds to the voltage range

Range 1, 2 is 128~544MHz maximum

Range 3: Maximum 128~330MHz

For the highest performance, use voltage level 1 and set PLLN=20

PLLP:1~128

PLLQ: 1~128

PLLR: 1 and even values

Voltage level, FLASH wait cycle setting

The voltage level must be set to 1, otherwise high-frequency operation will be abnormal.

LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);

HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);

The FLASH wait cycle must also be set to 4 or more.

HAL_RCC_ClockConfig(&pRCC_ClkInitStruct, FLASH_LATENCY_4);

The relationship between the FLASH wait cycle and the main frequency and voltage level is that the maximum is 160MHz and at least 4WS needs to be configured when the voltage level is 1.

The total code is as follows

#include "stm32u575xx.h"

#include "stm32u5xx_ll_gpio.h"

#include "stm32u5xx_ll_bus.h"

void SysTick_Handler(void)

{

static volatile uint32_t num = 0;

if(num++ >= 1000)

{

LL_GPIO_TogglePin(GPIOB, 1u<<7);

LL_GPIO_TogglePin(GPIOC, 1u<<7);

num=0;

}

HAL_IncTick();

}

void delay(uint32_t t)

{

volatile uint32_t timeout = t;

while(t--);

}

int main(void)

{

#if 1

LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);

HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);

RCC_OscInitTypeDef pRCC_OscInitStruct;

pRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;

pRCC_OscInitStruct.HSIState = RCC_HSI_ON;

pRCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;

pRCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;

pRCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

pRCC_OscInitStruct.PLL.PLLM = 1;

pRCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;

pRCC_OscInitStruct.PLL.PLLN = 20;

pRCC_OscInitStruct.PLL.PLLP = 1;

pRCC_OscInitStruct.PLL.PLLQ = 1;

pRCC_OscInitStruct.PLL.PLLR = 2;

pRCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_0;

pRCC_OscInitStruct.PLL.PLLFRACN = 0; /* */

HAL_RCC_OscConfig(&pRCC_OscInitStruct);

RCC_ClkInitTypeDef pRCC_ClkInitStruct;

pRCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;

pRCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

pRCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

pRCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;

pRCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

pRCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV2;

HAL_RCC_ClockConfig(&pRCC_ClkInitStruct, FLASH_LATENCY_4);

#endif

LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);

LL_GPIO_InitTypeDef GPIO_InitStruct;

//LL_GPIO_StructInit(&GPIO_InitStruct);

GPIO_InitStruct.Pin = LL_GPIO_PIN_7;

GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;

GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;

GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;

GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;

GPIO_InitStruct.Alternate = LL_GPIO_AF_0;

LL_GPIO_Init(GPIOB, &GPIO_InitStruct);

GPIO_InitStruct.Pin = LL_GPIO_PIN_7;

GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;

GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;

GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;

GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;

GPIO_InitStruct.Alternate = LL_GPIO_AF_0;

LL_GPIO_Init(GPIOC, &GPIO_InitStruct);

HAL_Init();

while(1)

{

///delay(1000000ul);

///LL_GPIO_TogglePin(GPIOB, 1u<<7);

}

}

Overclocking Test

160MHz

PLLN is set to 20

PLLN is set to 33, 8*33=264MHz, FLASH waiting time is set to FLASH_LATENCY_4

At this point the light can still be turned on OK, any further reduction of the FLASH wait time or increase of the PLLN will result in abnormal operation, so this should be the limit.

It can be seen that the overclocking range is quite large, and the FLASH wait period can be maintained at FLASH_LATENCY_4 after overclocking, indicating that the internal FLASH read performance also has a large margin.

Summarize

The above is a demonstration of RCC clock configuration, and an overclocking test was performed. As expected of a big manufacturer, it can still work after overclocking from 160M to 264M, and it can keep a small FLASH waiting cycle.

秦天qintian0303

How stable is the overclocking? How much can it be overclocked? Any advice?

qinyunti

Qintianqintian0303 posted on 2022-12-15 12:01 How is the overclocking stability? How much can it be overclocked? Is there any introduction?

The test in this article shows that the overclocking can be done to 264MHz, the FLASH wait cycle is 4, the lighting is OK, and no other peripherals are tested.

ICACHE is not tested, DCACHE is enabled for testing.

okhxyyo

Review summary: Free application | ST NUCLEO-U575ZI-Q https://en.eeworld.com/bbs/thread-1228653-1-1.html