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SparkRoad Review (8) - VGA Test [Copy link]

 

I have been doing this test for a while, and the vga test has not been successful. As a result of the test, I still recorded the process. As for the reason, I analyzed it for a long time but got no result.

Tested Hardware:

1. AOC 1080P monitor with VGA interface, frequency 1920*1080@75HZ, theoretically can meet the needs.

2. A VGA data cable, which should be considered brand new because I have never used the monitor since I bought it.

3. Anlu development board, USB cable

Because the display is 1920*1080P, check the source code and modify the parameters to:

The parameters of 1920x1080@60Hz 148.5MHz 44 148 1920 88 2200 5 36 1080 4 1125 are 44, 148, 1920...

`timescale 1ns/1ns
/* VGA参数配置表
************	clk		 	H_SYNC 		H_BACK 		H_DISP 		H_FRONT 	H_TOTAL 		V_SYNC 		V_BACK 		V_DISP 		V_FRONT 	V_TOTAL		*
640x480@60Hz	25.2MHz		96			48 			640 		16 			800 			2			33			480 		10			525		*
800x600@60Hz	40MHz		128			88 			800 		40 			1056			4			23			600 		1			628		*
1024x768@60Hz	65MHz		136			160 		1024 		24 			1344			6			29			768 		3			806		*
1280x720@60Hz	74.25MHz	40			220 		1280 		110			1650			5			20			720 		5			750		*
1280x1024@60Hz	108MHz		112			248 		1280 		48 			1688			3			38			1024		1			1066	*
1920x1080@60Hz	148.5MHz	44			148 		1920 		88 			2200			5			36			1080		4			1125	*
*/	
module Driver
#(
    parameter H_SYNC = 112	 , 		// 行同步信号时间
	parameter H_BACK = 248	 , 		// 行消隐后肩时间
	parameter H_DISP = 1280	 , 		// 行数据有效时间
	parameter H_FRONT = 48	 , 		// 行消隐前肩时间
	parameter H_TOTAL = 1688 , 		// 行扫描总时间
			
	parameter V_SYNC = 3	 , 		// 列同步信号时间
	parameter V_BACK = 38	 , 		// 列消隐后肩时间
	parameter V_DISP = 1024	 , 		// 列数据有效时间
	parameter V_FRONT = 1	 , 		// 列消隐前肩时间
	parameter V_TOTAL = 1066  		// 列扫描总时间	
)
(
	input  wire			clk,			//VGA clock
	input  wire			rst_n,     		//sync reset
	input  wire	[23:0]	lcd_data,		//lcd data
	
	//lcd interface
	output wire			lcd_dclk,   	//lcd pixel clock
	output wire			lcd_hs,	    	//lcd horizontal sync
	output wire			lcd_vs,	    	//lcd vertical sync
	output wire			lcd_en,			//lcd display enable
	output wire	[23:0]	lcd_rgb,		//lcd display data

	//user interface
	output wire	[11:0]	lcd_xpos,		//lcd horizontal coordinate
	output wire	[11:0]	lcd_ypos		//lcd vertical coordinate
);	
 
localparam	H_AHEAD = 	12'd1;

reg [11:0] hcnt; 
reg [11:0] vcnt;
wire lcd_request;

/*******************************************
		SYNC--BACK--DISP--FRONT
*******************************************/ 
//h_sync counter & generator
always @ (posedge clk or negedge rst_n)
begin
	if (!rst_n)
		hcnt <= 12'd0;
	else
	begin
        if(hcnt < H_TOTAL - 1'b1)		//line over			
            hcnt <= hcnt + 1'b1;
        else
            hcnt <= 12'd0;
	end
end 

assign	lcd_hs = (hcnt <= H_SYNC - 1'b1) ? 1'b0 : 1'b1; // line over flag

//v_sync counter & generator
always@(posedge clk or negedge rst_n)
begin
	if (!rst_n)
		vcnt <= 12'b0;
	else if(hcnt == H_TOTAL - 1'b1)	//line over
		begin
		if(vcnt == V_TOTAL - 1'b1)		//frame over
			vcnt <= 12'd0;
		else
			vcnt <= vcnt + 1'b1;
		end
end

assign	lcd_vs = (vcnt <= V_SYNC - 1'b1) ? 1'b0 : 1'b1; // frame over flag

// LED clock
assign	lcd_dclk = ~clk;

// Control Display
assign	lcd_en		=	(hcnt >= H_SYNC + H_BACK  && hcnt < H_SYNC + H_BACK + H_DISP) &&
						(vcnt >= V_SYNC + V_BACK  && vcnt < V_SYNC + V_BACK + V_DISP) 
						? 1'b1 : 1'b0;                   // Display Enable Signal
						
assign	lcd_rgb 	= 	lcd_en ? lcd_data : 24'h000000;	

//ahead x clock
assign	lcd_request	=	(hcnt >= H_SYNC + H_BACK - H_AHEAD && hcnt < H_SYNC + H_BACK + H_DISP - H_AHEAD) &&
						(vcnt >= V_SYNC + V_BACK && vcnt < V_SYNC + V_BACK + V_DISP) 
						? 1'b1 : 1'b0;
//lcd xpos & ypos
assign	lcd_xpos	= 	lcd_request ? (hcnt - (H_SYNC + H_BACK - H_AHEAD)) : 12'd0;
assign	lcd_ypos	= 	lcd_request ? (vcnt - (V_SYNC + V_BACK)) : 12'd0;

endmodule

At the same time, the parameters in Display were changed:

parameter H_DISP = 1280,

parameter V_DISP = 1024

The test started, but an error message was displayed: The signal cannot be supported

Then I tried 1024x768@60Hz 65MHz 1280x720@60Hz 74.25MHz, but the monitor still failed.

Only the default 1280x1024@60Hz can be displayed.

The image displayed is like this

Then: I modified the code of display.v. In theory, I should see a blue picture.

`timescale 1ns/1ns

// Define colors RGB--8|8|8
`define RED		24'hFF0000 
`define GREEN	24'h00FF00 
`define BLUE  	24'h0000FF 
`define WHITE 	24'hFFFFFF 
`define BLACK 	24'h000000 
`define YELLOW	24'hFFFF00 
`define CYAN  	24'hFF00FF 
`define ROYAL 	24'h00FFFF 

// Define Display Mode
// `define	VGA_HORIZONTAL_COLOR
// `define	VGA_VERTICAL_COLOR
// `define	VGA_GRAY_GRAPH
`define	VGA_GRAFTAL_GRAPH

module Display
#(
	parameter H_DISP = 1280,
	parameter V_DISP = 1024
)
( 
	input  wire	 		clk,	
	input  wire			rst_n,	
	input  wire	[11:0]	lcd_xpos,	//lcd horizontal coordinate
	input  wire	[11:0]	lcd_ypos,	//lcd vertical coordinate
	
	output reg  [23:0]	lcd_data	//lcd data
);

`ifdef VGA_HORIZONTAL_COLOR
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		lcd_data <= 24'h0;
	else
		begin
//		if	(lcd_ypos >= 0 && lcd_ypos < (V_DISP/8)*1)
//			lcd_data <= `RED;
//		else if(lcd_ypos >= (V_DISP/8)*1 && lcd_ypos < (V_DISP/8)*2)
//			lcd_data <= `GREEN;
//		else if(lcd_ypos >= (V_DISP/8)*2 && lcd_ypos < (V_DISP/8)*3)
//			lcd_data <= `BLUE;
//		else if(lcd_ypos >= (V_DISP/8)*3 && lcd_ypos < (V_DISP/8)*4)
//			lcd_data <= `WHITE;
//		else if(lcd_ypos >= (V_DISP/8)*4 && lcd_ypos < (V_DISP/8)*5)
//			lcd_data <= `BLACK;
//		else if(lcd_ypos >= (V_DISP/8)*5 && lcd_ypos < (V_DISP/8)*6)
//			lcd_data <= `YELLOW;
//		else if(lcd_ypos >= (V_DISP/8)*6 && lcd_ypos < (V_DISP/8)*7)
//			lcd_data <= `CYAN;
//		else
//			lcd_data <= `ROYAL;

		if	(lcd_ypos >= 0 && lcd_ypos < (V_DISP/8)*1)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*1 && lcd_ypos < (V_DISP/8)*2)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*2 && lcd_ypos < (V_DISP/8)*3)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*3 && lcd_ypos < (V_DISP/8)*4)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*4 && lcd_ypos < (V_DISP/8)*5)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*5 && lcd_ypos < (V_DISP/8)*6)
			lcd_data <= `BLUE;
		else if(lcd_ypos >= (V_DISP/8)*6 && lcd_ypos < (V_DISP/8)*7)
			lcd_data <= `BLUE;
		else
			lcd_data <= `BLUE;
         
		
        end
end
`endif

`ifdef VGA_VERTICAL_COLOR
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		lcd_data <= 24'h0;
	else
		begin
//		if	(lcd_xpos >= 0 && lcd_xpos < (H_DISP/8)*1)
//			lcd_data <= `RED;
//		else if(lcd_xpos >= (H_DISP/8)*1 && lcd_xpos < (H_DISP/8)*2)
//			lcd_data <= `GREEN;
//		else if(lcd_xpos >= (H_DISP/8)*2 && lcd_xpos < (H_DISP/8)*3)
//			lcd_data <= `BLUE;
//		else if(lcd_xpos >= (H_DISP/8)*3 && lcd_xpos < (H_DISP/8)*4)
//			lcd_data <= `WHITE;
//		else if(lcd_xpos >= (H_DISP/8)*4 && lcd_xpos < (H_DISP/8)*5)
//			lcd_data <= `BLACK;
//		else if(lcd_xpos >= (H_DISP/8)*5 && lcd_xpos < (H_DISP/8)*6)
//			lcd_data <= `YELLOW;
//		else if(lcd_xpos >= (H_DISP/8)*6 && lcd_xpos < (H_DISP/8)*7)
//			lcd_data <= `CYAN;
//		else
//			lcd_data <= `ROYAL;

		if	(lcd_xpos >= 0 && lcd_xpos < (H_DISP/8)*1)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*1 && lcd_xpos < (H_DISP/8)*2)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*2 && lcd_xpos < (H_DISP/8)*3)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*3 && lcd_xpos < (H_DISP/8)*4)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*4 && lcd_xpos < (H_DISP/8)*5)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*5 && lcd_xpos < (H_DISP/8)*6)
			lcd_data <= `BLUE;
		else if(lcd_xpos >= (H_DISP/8)*6 && lcd_xpos < (H_DISP/8)*7)
			lcd_data <= `BLUE;
		else
			lcd_data <= `BLUE;
       
		end
end
`endif

`ifdef VGA_GRAFTAL_GRAPH
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		lcd_data <= 24'h0;
	else
		lcd_data <= lcd_xpos * lcd_ypos;
end
`endif


`ifdef VGA_GRAY_GRAPH
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		lcd_data <= 24'h0;
	else
		begin
		if(lcd_ypos < V_DISP/2)
			lcd_data <= {lcd_ypos[7:0], lcd_ypos[7:0], lcd_ypos[7:0]};
		else
			lcd_data <= {lcd_xpos[7:0], lcd_xpos[7:0], lcd_xpos[7:0]};
		end
end
`endif

endmodule

Then the picture didn’t change.

Later, I tried other colors and it was the same. I really don't know why. I have no clue at all looking at the source code.

This post is from Domestic Chip Exchange

Latest reply

The routine uses a resolution of 1280*1024 by default, so its clk_vga clock uses 108MHz. If you change other resolutions, clk_vga needs to be changed to the corresponding frequency, for example, 1920*1080 requires a 148.5MHz clock. [attach]611685[/attach] clk_vga multiplies clk_24m to 108MHz through PLL, so if you want to change the resolution, in addition to modifying the parameters in the Driver, you also need to modify Clk_div to make the clock frequency match the resolution. [attach]611686[/attach]   Details Published on 2022-6-7 13:02
 
 

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Has the PLL clock been modified? In theory, different resolutions correspond to different clocks

This post is from Domestic Chip Exchange

Comments

It should not be necessary, the program can be set according to the fixed clock  Details Published on 2022-6-6 17:28
 
 
 

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littleshrimp posted on 2022-6-6 14:25 Has the PLL clock been modified? In theory, different resolutions correspond to different clocks

It should not be necessary, the program can be set according to the fixed clock

This post is from Domestic Chip Exchange

Comments

Has the VGA clock been modified?  Details Published on 2022-6-7 13:02
Has the VGA clock been modified?  Details Published on 2022-6-6 18:29
 
 
 

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bigbat posted on 2022-6-6 17:28 It shouldn't be necessary, the program can be set according to the fixed clock

Has the VGA clock been modified?

This post is from Domestic Chip Exchange
 
 
 

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bigbat posted on 2022-6-6 17:28 It should not be necessary, the program can be set according to the fixed clock

The routine uses a resolution of 1280*1024 by default, so its clk_vga clock uses 108MHz. If you change other resolutions, clk_vga needs to be changed to the corresponding frequency, for example, 1920*1080 requires a 148.5MHz clock.

clk_vga multiplies clk_24m to 108MHz through PLL, so if you want to change the resolution, in addition to modifying the parameters in the Driver, you also need to modify Clk_div to make the clock frequency match the resolution.

This post is from Domestic Chip Exchange

Comments

Thanks for the tip  Details Published on 2022-6-7 13:08
Thanks for the tip  Details Published on 2022-6-7 13:04
Personal signature虾扯蛋,蛋扯虾,虾扯蛋扯虾
 
 
 

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littleshrimp posted on 2022-6-7 13:02 The routine uses a resolution of 1280*1024 by default, so its clk_vga clock uses 108MHz. If you change the resolution to another one, clk_v ...

Thanks for the tip

This post is from Domestic Chip Exchange
 
 
 

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littleshrimp posted on 2022-6-7 13:02 The routine uses a resolution of 1280*1024 by default, so its clk_vga clock uses 108MHz. If you change the resolution to another one, clk_v ...

Thank you. Last time you suggested to change the clock frequency, I also looked at the program but didn't find any place to change the frequency. I thought I could just change the parameters. I will take a closer look at the program later.

This post is from Domestic Chip Exchange
 
 
 

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