Blue line appears in vhdl bidirectional bus buffer simulation

洽洽香瓜子

The original code is as follows:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bio_buffer IS
PORT(a,b:INOUT STD_LOGIC;
en,dr :IN STD_LOGIC
);
END ENTITY;

ARCHITECTURE behaver OF bio_buffer IS
SIGNAL aout: STD_LOGIC;
SIGNAL bout: STD_LOGIC;
BEGIN
PROCESS(a,dr,en)
BEGIN
IF((en='0')AND(dr='1')) THEN bout<=a;
ELSE bout<='Z';
END IF;
b<=bout;
END PROCESS;
PROCESS(b,dr,en)
BEGIN
IF((en='0')AND(dr='0'))THEN aout<=b ;
ELSE aout<='Z';
END IF;
a<=aout;
END PROCESS;
END ARCHITECTURE;
The simulation results are as follows:

It can be seen that after the input signal a is changed, the bout used to take over the input signal value is assigned correctly, and the statement b<=bout is also written. Why is the b signal always in a high-impedance state? God answers.

bigbat

The HDL language is not enough, it is all about describing the "circuit". As long as you burn it into the chip, the circuit will be working regardless of whether you use it or not. This is where all your problems lie. Include your last question.

洽洽香瓜子

bigbat published on 2022-4-26 13:34 The HDL language is not enough, it is all about describing the "circuit". As long as you burn it into the chip, the circuit is still working regardless of whether you use it...

I am a beginner, and I am still practicing the language and the use of EDA software. I have not yet touched the burning into the chip you mentioned, so I can only ask some simulation-related questions. Can the specific code be included in the chip? Producing correct results is currently not accessible.

bigbat

What I emphasize to you is burning into the chip because during simulation, some delays or some instructions that cannot be synthesized can be executed. This does not mean that there will be no logic errors in the simulation. If the simulation is so unreliable, then there is no need to simulate it. .

洽洽香瓜子

bigbat published on 2022-4-27 09:00 What I emphasize to you is burning into the chip because during simulation, some delays or some instructions that cannot be synthesized can be executed. This does not mean that simulation will not occur...

What you mean is that the simulation error may not be due to logic problems in the code, but some problems related to the simulation environment. Is my understanding correct?

洽洽香瓜子

The problem has been solved. Knowledge point: When simulating the INOUT port, it should be initialized to 'Z'. At the same time, after assigning a value to this type of port, it should be restored to the 'Z' state immediately, otherwise it will affect the data on the bus. Reading (internal data is written to the bus, code assignment is also equivalent to writing to the bus, which is equivalent to assigning two different values to the same signal, and an unsteady state will occur).

Tienld2

Your code write not good. IF you used define Z logic output, out put is Z logic.