[GD32E503 Review] + Unboxing and Schematic Diagram
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Fig 1 Outer packaging
Fig 2 Schematic diagram of the first look after unpacking
The development board packaging list is as follows:
Development board GD32E503V-EVA , quantity 1 ;
USB A type to USB Micro B cable, quantity 2 ;
Fig 3 Schematic diagram of the development board packaging list
From the packing list, there are two identical 5V USB cables, which may be used for power supply and debugging connection. But I still have questions in my heart: how to power the development board, how to debug the connection, and how to build the development environment? First, learn the schematic diagram by referring to the board.
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Fig 4 Development board power supply chip diagram
Where does the power +5V or signal +U5V come from?
- +5V is only in the position shown above
- +U5V two interfaces, from two locations: CN100 , CN2
Fig 5 +U5V power supply interface diagram
It seems that the development board needs to be powered on by connecting CN100 or CN2 .
Since debugging does not require offline work, the default power supply for GD32E503VET6 (U1) is +3V3 power supply converted by AMS1117 ( U2 ). At the same time, pay attention to the jumper of the development board - short JP0 ( 1 , 2 ).
Fig 6 Chip GD32E503VET6 power supply interface diagram
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Fig 7 Startup mode interface diagram
GD32E503VET6 has two boot modes: BOOT0 and BOOT1 ( PB2 ).
Fig 8 Diagram of the default startup mode of the development board
The following table summarizes the silk screen printing from the above figure:
Tab 1 development board boot mode silkscreen description list
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BOOT1
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BOOT0
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MODE
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ANY
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2-3
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USER
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2-3
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1-2
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System
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1-2
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1-2
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SRAM
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But the jumpers on the development board are like this: JP2 ( 2 , 3 ) and JP3 ( 2 , 3 ) are short-circuited. According to the table above, it should belong to " USER " MODE . What does this mean? Let's first check the GD32E503VET6 specification. For details, see: https://www.gigadevice.com/zh-hans/microcontroller/gd32e503vet6/
There are three ways to start GD32E503VET6 :
- Main flash memory (default)
- System memory
- On-chip SRAM
The boot loader is located in the system's internal boot memory ROM storage chip. The Flash storage is usually reprogrammed through USART0 ( PA9 and PA10 ) or USART1 ( PA2 and PA3 ) .
This development board only uses USART0 and does not develop USART1 .
Fig 9 Development board USART0 schematic diagram
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Fig 10 Schematic diagram of powering on the CN100 development board
- CN2 power on
Fig 11 Schematic diagram of powering on CN2 of the development board
Judging from the initial power-on results, the development board functions normally and can be further tested.
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- Development board user signal statistics
According to the schematic diagram, the user signal list of the development board is summarized as follows:
Tab 2 development board user signal list
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serial number
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Signal name
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describe
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Interface Location
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Remark
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1
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ADC012_IN1 ( PA1 )
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AD, 0-3.3V, adjustable by sliding rheostat
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|
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2
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ADC012_IN2 ( PA2 )
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AD , Pin2
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JP4
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Pin1 and JP7 , pin1 directly connected
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3
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DAC_OUT0 ( PA4 )
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DA , pin1
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JP7
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Pin3.GND
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4
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DAC_OUT1 ( PA5 )
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DA , pin2
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JP7
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Pin3.GND
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5
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LED1(PC0)
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LED1,0603
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|
|
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6
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LED2(PC2)
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LED2,0603
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|
|
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7
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LED3(PE0)
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LED3,0603
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|
|
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8
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LED4(PE1)
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LED4,0603
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9
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Extensions
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External expansion interface JP8
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JP8
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10
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Extensions
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External expansion interface JP9
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JP9
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11
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Extensions
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External expansion interface JP10
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JP10
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12
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Extensions
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External expansion interface JP11
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JP11
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|
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13
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KEY A(PA0)
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Button , K1-1506SN-01, pin 1 (A), pull up to 3.3V
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K2
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Pin4(COM), GND
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14
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KEY B(PC13)
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Button , K1-1506SN-01, pin 2 (B), pull up to 3.3V
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K2
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Pin4(COM), GND
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15
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KEY C(PB14)
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Button , K1-1506SN-01, pin 3 (C), pull up to 3.3V
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K2
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Pin4(COM), GND
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16
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KEY D(PC5)
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Button , K1-1506SN-01, pin 5 (D), pull up to 3.3V
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K2
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Pin4(COM), GND
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17
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KEY Cet(PC4)
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Button , K1-1506SN-01, pin 6 (Cet), pull up 3.3V
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K2
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Pin4(COM), GND
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18
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GD-Link
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On-chip integrated resources GD-Link
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CN100
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19
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I2C0_SCL(PB6)
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SCL, pin6, I2C, AT24C02C-SSHM-T(U4)
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|
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20
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I2C0_SCA(PB7)
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SCA, pin5, I2C, AT24C02C-SSHM-T(U4)
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twenty one
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I2S_SD(PB15)
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SDIN,pin1,I2S,CS4344(U10)
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J3
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HeadPhone
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twenty two
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I2S_CK(PB13)
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SCLK,pin2,I2S,CS4344(U10)
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J3
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HeadPhone
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twenty three
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I2S_WS(PB12)
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LRCK,pin3,I2S,CS4344(U10)
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J3
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HeadPhone
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twenty four
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I2S_MCK(PC6)
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MCLK,pin4,I2S,CS4344(U10)
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J3
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HeadPhone
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25
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JTAG
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JP1
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|
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26
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BOOT0
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BOOT0, pin94, GD32E503VET6(U1)
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JP2,pin2
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Pin3 GND, pin3 is directly connected to pin2
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27
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BOOT1
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BOOT1, pin37(PB2), GD32E503VET6(U1)
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JP3,pin2
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Pin3 GND, pin3 is directly connected to pin2
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28
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NRST
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Reset button , K-1102B, pull up 3.3V , high by default, low level when reset , pin14, GD32E503VET6 (U1)
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K1
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29
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VBAT
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Chip powered, onboard electronics or power chip powered
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JP0
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|
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30
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TFCAD
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SDIO
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JP21
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31
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SPI
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GD25Q16(U5)
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JP12
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Short JP12(1,2) for DAC; Short JP12(3,2) for SPI0;
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32
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USART0 To USB
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CH340E(U3)
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J1
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33
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CN2
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