Detailed explanation of MSP430 crystal oscillator configuration

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Detailed explanation of MSP430 crystal oscillator configuration [Copy link]

Compared with MSP430 (F149), MSP430 (F5529) has more powerful functions.

UCS Introduction
The UCS of the MSP430F5XX/MSP430F6XX series devices contains five clock sources, namely: XT1CLK, VLOCLK, REFOCLK, DCOCLK and XT2CLK. For a detailed introduction to these five clocks, please refer to the instruction manual of this series of chips. Among them, XT1CLK, VLOCLK, REFOCLK and XT2CLK are not much different from the MSP430F1XX series, and learning and configuring them is also relatively simple.

UCS power-on default state

After PUC, the default state of the UCS module is as follows:

1. (1) XT1 is in LF mode as the XT1CLK clock source. ACLK is selected as XT1CLK.
2. (2) MCLK is selected as DCOCLKDIV
3. (3) SMCLK is selected as DCOCLKDIV
4. (4) FLL is enabled and XT1CLK is used as the FLL reference clock.
5. (5) The XIN and XOUT pins are set as general IO. Before XIN and XOUT are configured as XT1 functions, XT1 remains disabled.
6. (6) If available, XT2IN and XT2OUT are set as general purpose IOs and remain disabled.

It is very important to understand the default state of UCS power-on, which is very important for understanding the subsequent configuration logic.

UCS clock source switching

Since REFOCLK, VLOCLK, and DCOCLK (here we temporarily assume) are available in the default state, when switching, you only need to configure the clock sources of ACLK, SMCLK, and MCLK through UCSCTL4, while XT1CLK and XT2CLK need to be determined according to the specific configuration of the hardware. Therefore, the configuration of these two is somewhat different from the first three. Next, we will do three experiments:

(1) Configure MCLK and SMCLK with REFOCLK and VLOCLK
REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK. The specific code is as follows:

1. #include<msp430f5529.h>
4. voidmain(void){
5. WDTCTL=WDTPW+WDTHOLD;
7. P1SEL |= BIT0;
8. P1DIR |= BIT0; //Measure ACLK
9. P2SEL|=BIT2;
10. P2DIR |= BIT2; //Measure SMCLK
11. P7SEL |= BIT7;
12. P7DIR |= BIT7; //Measure MCLK
15. //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK
16. UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK
19. while(1);
20. }

The above code implements the switch of SMCLK and MCLK to VLOCLK and REFOCLK. The operation of ACLK is the same, so no further explanation is given.
(2) Configure MCLK and SMCLK to XT1CLK

The development board XT1 I have is connected to a 32.768K watch clock crystal. The configuration of XT1CLK is divided into the following steps:

1. 1. Configure IO ports 5.4 and 5.5 to XT1 function.
2. 2. Configure XCAP to XCAP_3, which is a 12PF capacitor.
3. 3. Clear the XT1OFF flag.
4. 4. Wait for XT1 to start oscillating.

The specific code is as follows:

1. #include<msp430f5529.h>
3. voidmain(void){
4. WDTCTL=WDTPW+WDTHOLD;
6. P1SEL |= BIT0;
7. P1DIR |= BIT0; //Measure ACLK
8. P2SEL|=BIT2;
9. P2DIR |= BIT2; //Measure SMCLK
10. P7SEL |= BIT7;
11. P7DIR |= BIT7; //Measure MCLK
13. P5SEL |= BIT4|BIT5; //Configure IO as XT1 function
14. UCSCTL6 |= XCAP_3; //Configure the capacitor to 12pF
15. UCSCTL6 &= ~XT1OFF; // Enable XT1
17. while(SFRIFG1&OFIFG){
18. UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear three types of clock flags
19. // Here we need to clear three flags, because any
20. // The flag bit will set OFIFG
21. SFRIFG1 &= ~OFIFG; // Clear the clock error flag
22. }
23. UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_0|SELM_0; //Configure SMCLK and MCLK clock sources to XT1
24. while(1);
25. }

(3) Configure SMCLK and MCLK to XT2
The process of configuring SMCLK and MCLK to XT2 is basically the same as that of configuring them to XT1. The only difference is that before configuring SMCLK and MCLK to XT2, the clock sources of ACLK and REFCLK need to be changed. Because the default clock source of ACLK and REFCLK is XT1, and we have not configured to start XT1CLK, an XT1 clock error will occur, namely XT1LFFG. Therefore, we first configure ACLK and REFCLK to the chip's own clock (REFOCLK or VLOCLK) or the clock to be started (XT2). In addition, capacitors do not need to be configured when configuring XT2. Therefore, the code for configuring SMCLK and MCLK to XT2 is as follows:

1. #include<msp430f5529.h>
3. voidmain(void){
4. WDTCTL=WDTPW+WDTHOLD;
6. P1SEL |= BIT0;
7. P1DIR |= BIT0; //Measure ACLK
8. P2SEL|=BIT2;
9. P2DIR |= BIT2; //Measure SMCLK
10. P7SEL |= BIT7;
11. P7DIR |= BIT7; //Measure MCLK
13. P5SEL |= BIT2|BIT3; //Configure IO as XT2 function
14. UCSCTL6 &= ~XT2OFF; // Enable XT2
16. UCSCTL4 = UCSCTL4&(~(SELA_7))|SELA_1; //Configure ACLK as VLOCLK first
17. UCSCTL3 |= SELREF_2; //Configure REFCLK to REFCLK
19. while(SFRIFG1&OFIFG){
20. UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear three types of clock flags
21. // Here we need to clear three flags, because any
22. // The flag bit will set OFIFG
23. SFRIFG1 &= ~OFIFG; // Clear the clock error flag
24. }
25. UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_5|SELM_5; //Configure SMCLK and MCLK clock sources to XT2
26. while(1);
27. }

After completing the previous three experiments, we can master the basic operation of the MSP430F5XX series clock switching. It is not explained in detail. If you have any other questions, please read the chip manual carefully or leave a message for discussion.
Detailed explanation of the DCO module
The DCO module is very important in the MSP430F5XX series chips, because starting from MSP430F4XX, MSP430 has referenced the FLL module, which is a phase-locked loop. It can increase the system clock frequency by multiplying the frequency, thereby increasing the system's operating speed.
The DCO module requires a reference clock REFCLK to operate. REFCLK can come from REFOCLK, XT1CLK, and XT2CLK. It is selected by SELREF of UCSCTL3. The default XT1CLK is used, but if XT1CLK is not available, REFOCLK is used.
The DCO module has two output clock signals, DCOCLK and DCOCLKDIV. The multiplication calculation formula is as follows:

1. DCOCLK = D*(N+1)*(REFCLK/n)
2. DCOCLKDIV = (N+1)*(REFCLK/n)

Among them:
n is the REFCLK input clock division, which can be set by FLLCLKDIV in UCSCTL3, and the default is 0, that is, no division;
D can be set by FLLD in UCSCTL2, and the default is 1, that is, 2 division;
N can be set by FLLN in UCSCTL2, and the default is 32.
Therefore, if no settings are made after the system is powered on, the actual value of DCOCLK is 2097152, and the actual value of DCOCLKDIV is 1048576.
In addition, DCORSEL and DCOx need to be configured to configure the chip operating frequency. The specific functions of DCORSEL and DCOx are as follows:
DCORSEL is located in bits 4 to 6 of the UCSCTL1 control register, a total of 3 bits, which divides the DCO into 8 frequency segments.
DCOx is located in bits 8 to 12 of UCSCTL0, a total of 5 bits, which divides the frequency segment selected by DCORSEL into 32 frequency levels, each level is about 8% higher than the previous level. The register system can be automatically adjusted and is usually configured to 0.
The specific role of DCORSEL and DCOx values can be found in the MSP430F5529 data sheet. Reading the relevant section of the manual, you can find the following table:

It can be seen that the frequency adjustment range of DCORESL is as follows:

1. The adjustment range of DCORSEL = 0 is about 0.20~0.70MHZ;
2. The adjustment range of DCORSEL = 1 is about 0.36~1.47MHZ;
3. The adjustment range of DCORSEL = 2 is about 0.75~3.17MHZ;
4. The adjustment range of DCORSEL = 3 is about 1.51~6.07MHZ;
5. The adjustment range of DCORSEL = 4 is about 3.2~12.3MHZ;
6. The adjustment range of DCORSEL = 5 is about 6.0~23.7MHZ;
7. The adjustment range of DCORSEL = 6 is about 10.7~39.7MHZ;
8. The adjustment range of DCORSEL = 7 is about 19.6~60MHZ.

After understanding the above, you can understand the code in TI's official example. The relevant parts of the official code are as follows:

1. if(fsystem<=630)//fsystem<0.63MHz
2. UCSCTL1=DCORSEL_0;
3. elseif(fsystem<1250)//0.63MHz<fsystem<1.25MHz
4. UCSCTL1=DCORSEL_1;
5. elseif(fsystem<2500)//1.25MHz<fsystem<2.5MHz
6. UCSCTL1=DCORSEL_2;
7. elseif(fsystem<5000)//2.5MHz<fsystem<5MHz
8. UCSCTL1=DCORSEL_3;
9. elseif(fsystem<10000)//5MHz<fsystem<10MHz
10. UCSCTL1=DCORSEL_4;
11. elseif(fsystem<20000)//10MHz<fsystem<20MHz
12. UCSCTL1=DCORSEL_5;
13. elseif(fsystem<40000)//20MHz<fsystem<40MHz
14. UCSCTL1=DCORSEL_6;
15. else
16. UCSCTL1=DCORSEL_7;

All of them are within the range mentioned above. Since there are overlaps in the previous ranges, the values in the sample code are reasonable values selected by TI engineers based on the above parameters.
At this point, I believe that everyone can understand the principles of the DCO configuration related parts with the chip manual and this article. The following is the detailed code to select XT1 as the DCO reference clock and multiply the DCOCLK frequency to 25M:

1. #include<msp430f5529.h>
3. voiddelay(){
4. volatileunsignedinti;
5. for(i=0;i!=5000;++i){
6. _NOP();
7. }
8. }
10. voidSetVcoreUp(unsignedintlevel)
11. {
12. //OpenPMMregistersforwrite
13. PMMCTL0_H=PMMPW_H;
14. //SetSVS/SVMhighsidenewlevel
15. SVSMHCTL=SVSHE+SVSHRVL0*level+SVMHE+SVSMHRRL0*level;
16. //SetSVMlowsidetonewlevel
17. SVSMLCTL=SVSLE+SVMLE+SVSMLRRL0*level;
18. //WaittillSVMissettled
19. while((PMMIFG&SVSMLDLYIFG)==0);
20. //Clearalreadysetflags
21. PMMIFG&=~(SVMLVLRIFG+SVMLIFG);
22. //SetVCoretonewlevel
23. PMMCTL0_L=PMMCOREV0*level;
24. //Waittillnewlevelreached
25. if((PMMIFG&SVMLIFG))
26. while((PMMIFG&SVMLVLRIFG)==0);
27. //SetSVS/SVMlowsidetonewlevel
28. SVSMLCTL=SVSLE+SVSLRVL0*level+SVMLE+SVSMLRRL0*level;
29. //LockPMMregistersforwriteaccess
30. PMMCTL0_H=0x00;
31. }
33. voidmain(void){
34. WDTCTL=WDTPW+WDTHOLD;
35. P1SEL&=~BIT1;
36. P1DIR |= BIT1;
38. P1SEL |= BIT0; //ACLK
39. P1DIR |= BIT0;
40. P2SEL|=BIT2;//SMCLK
41. P2DIR|=BIT2;
42. P7SEL |= BIT7; //MCLK
43. P7DIR |= BIT7;
45. P5SEL |= BIT4|BIT5;
46. UCSCTL6|=XCAP_3;
47. UCSCTL6&=~XT1OFF;
49. SetVcoreUp(1); //Increase the Vcore voltage level once, please refer to the manual for details
50. SetVcoreUp(2);
51. SetVcoreUp(3);
53. __bis_SR_register(SCG0);
54. UCSCTL0 = 0;
55. UCSCTL1=DCORSEL_6;
56. UCSCTL2=FLLD_1|380;
57. __bic_SR_register(SCG0);
58. __delay_cycles(782000);
60. /*
61. * By default: ACLK=FLLREFCLK=XT1 SMCLK=MCLK=DCOCLKDIV XT2 is off
62. * To avoid XT1LFOFFG, set ACLK and FLLREFCLK to REFOCLK
63. * And turn on XT2OFF, otherwise XT2 will be unusable
64. **/
65. //UCSCTL6&=~(XT2DRIVE0|XT2DRIVE1|XT2OFF);
67. while(SFRIFG1&OFIFG){//CheckOFIFGfaultflag
68. UCSCTL7&=~(XT2OFFG+XT1LFOFFG+DCOFFG);//ClearOSCflautFlags
69. SFRIFG1&=~OFIFG;//ClearOFIFGfaultflag
70. }
72. UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_3|SELM_3;
74. while(1){
75. P1OUT^=BIT1;
76. delay();
77. }
78. }