A few pictures help you easily understand DDR crosstalk

yvonneGan

A few pictures help you easily understand DDR crosstalk [Copy link]

Original article by Mr. High Speed | Huang Gang

If you are asked to evaluate the crosstalk of high-speed serial signals, you will say that their crosstalk is below -40db and has no effect. But if you are asked to evaluate the crosstalk of parallel signals such as DDR, you will say that the crosstalk between DQ0 and DQ1 is -30db, the crosstalk between DQ1 and DQ2 is -25db, and the crosstalk between DQ2 and DQ3... You can count slowly, I am leaving first.

According to past experience, everyone will come to work in the company with a heavy heart today. Mr. Gaosu also expressed his deep understanding. Therefore, today's article is very concise and vivid, so as to satisfy everyone's desire not to use their brains too much today. I remember that the topic of artificial intelligence was mentioned in the previous articles. Let's continue to talk about some technical things. In the rapid rise of artificial intelligence, the DDR module as the core computing power has undoubtedly become very popular. Because in the pursuit of ultra-large computing power, people have higher and higher requirements for the capacity and rate of DDR. The computing power cards that Mr. Gaosu has come into contact with are getting smaller and smaller, but there is a trend of more and more DDR modules in the board, with 4 channels, 8 channels, or even more. Moreover, while the number of particles continues to increase, the speed we require is basically getting higher and higher, basically starting at 2400Mbps, and the highest has been 3200Mbps. In addition, the board density is getting smaller and smaller. From the various DDR designs we have come into contact with in the past year or so, it is no exaggeration to say that the difficulty of DDR design may have exceeded many people's imagination...

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Colleagues who have worked on DDR design know that under very dense particle arrangement, it may take a lot of effort to successfully pull out all the signals. After the conduction, you have to hold your hands steady to make the equal length (5mil, 2mil, we have seen customers ask for 1mil...), and when you think you can finish the work, the customer will ask you if your spacing can be increased a little bit with an attitude that looks like he is negotiating with you.

OK... Our design engineers are very rigorous, and they love to be able to increase the spacing by 1mil, although they may not know what the use of the 1mil that they have worked so hard to increase is, just like the use of the 2mil equal length that they have worked so hard to make when they are doing equal length. The

general result is like this: after our engineers have been struggling, the time is almost up, and the customers finally understand the pain of our engineers. Everyone finally forced a consensus: thank you for your hard work, or let's just leave it like this. Finally, there is no need to make more stringent equal lengths, and finally there is no need to increase the spacing by 0.5mil. Although the customer is thinking: Actually, we can continue...

The equal length is done, and the spacing seems to be as wide as possible. We give it to our SI members for simulation. In our eyes, the result of such a set of data signals is already very good. It is probably like this:
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From the aperture of this set of data signal eye diagrams, the margin of the entire high and low levels is very large. Such an eye diagram will definitely pass in actual debugging. But if I mark some points and let everyone look at the same eye diagram again, you may feel a little surprised: Why is my equal length 2mil, and the spacing has been stretched to the point where it can't be opened any further, but the delay of this set of data is actually 50ps different (blue mask in the figure below), and the amplitude oscillation of the level is also more than 100mV (red mask in the figure below).
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The data signal is strictly point-to-point. Our impedance is 40 ohms, and the ODT of our chip driver and chip receiver is also 40 ohms. This shows that such delay and level oscillation are not caused by reflections from impedance mismatch (at least not for the most part). At this time, we focus on the crosstalk that is difficult to analyze.

From our professional point of view, it is indeed the crosstalk that should be blamed. We will not talk about some very complicated theories and formulas here. We will only use the following pictures to let everyone understand how crosstalk affects our level oscillation and delay.

There will be 3 transmission modes for two adjacent lines, which are as follows:
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Then after the attack signal reaches the receiving end, their results are as follows:

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Here are the answers to two questions you may want to ask:

1. Why are the arrival times different? The common mode speed is slow, the differential mode speed is fast, and the stationary mode is in the middle. Because under the influence of the common mode, the capacitance between the two lines is the weakest; under the influence of the differential mode, the capacitance of the two lines is the strongest. At this time, it is like a differential line, and the two lines refer to each other, so the transmission delay is the fastest.

2. Why are the level amplitudes different? Similarly, when in common mode, the levels of the two lines are in the same direction, complement each other, and the amplitude is high; when in differential mode, the levels of the two lines are in opposite directions, cancel each other out, and the amplitude is reduced.

So when the two lines run different random code patterns, it is not surprising that you see the signal of one of the lines as shown below.

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Let's go back to the DDR data signal above. It is more complicated for them. A group of 8 DQ plus DM signals have different code types. The crosstalk between them causes their eye diagrams to show different delays and level oscillations. In fact, the theory may be very complicated, but its manifestation is like this. In short, for the crosstalk of parallel signals like DDR, it is more intuitive and convincing to analyze it from the perspective of time domain. Of course, the difficulty is also here. You must analyze the entire group of signals and even the signals of the entire channel together to maximize the crosstalk effect. Therefore

, we made 5mil or even smaller equal lengths, which is really insignificant compared to the 50ps of the simulation waveform above. In fact, crosstalk will indeed have a more serious impact in DDR modules. Just imagine that we think 5mV of crosstalk is very large in high-speed serial signals, but in DDR modules, there can be hundreds of mV. Of course, there are still big differences between the two. The eye diagram margin of high-speed serial signals is still much smaller than that of DDR, generally only within 100mV. The high and low level margins of our current DDR system are several hundred mV, and the DDR rate also determines that the loss of the routing has little effect on it.

This content is originally created by yvonneGan , a netizen of EEWORLD forum . If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source.

Therefore, we can still accept the crosstalk result of 100mV, and from the perspective of the entire waveform, the margin is still large. However, as the DDR level becomes lower and lower, the corresponding margin will definitely become smaller and smaller, and then the crosstalk may have a serious impact.

蓝天007

I learned something, thanks for sharing!

generalcircuits

Thanks for sharing, I'm learning

A few pictures help you easily understand DDR crosstalk [Copy link]

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