Detailed explanation of the connection technology between CF card and CPLD in ARM embedded system
[Copy link]
With the continuous improvement of application requirements, many embedded systems require extended large-capacity storage to store data when applied. CF cards (Compact Flash Cards) are widely used in embedded products due to their low price, large storage capacity, small size, good compatibility and other advantages. However, the existing CF card interface circuit has the disadvantages of complex interface and low stability, which cannot meet the needs of customers. Through in-depth research on the working principle of the external bus interface (EBI) of the ARM processor AT91RM9200, CF card and CPLD, it is proposed to use CPLD to improve the CF card interface circuit to solve the shortcomings of the existing interface circuit.
2 Device Introduction
2.1 External Bus Interface
The system uses the AT91RM9200 with ARM920T as the core as the microprocessor. It is a system built completely around the ARM920T Thumb processor. It has a wealth of system and application peripherals and standard interfaces, including a high-speed on-chip SRAM work area and a low-latency external bus interface (EBI) to complete the seamless connection between the off-chip storage area and the internal memory mapping peripheral configuration required by the application. The external bus interface structure is shown in Figure 1.
EBI supports CF card and SmartMedia protocol through integrated circuits, which greatly reduces the need for external components. In addition, EBI can handle data transfer of up to 8 peripherals, each of which is assigned 8 address spaces defined in the built-in storage controller. Data is transmitted through a 16-bit or 32-bit data bus, the address bus is up to 26 bits, and 8 chip select ports (NCS［7:0］) and multiple control pins are multiplexed between different external storage controllers.
2.2 CF Card
CF Card (Compact Flash Card) is a memory card using Flash Memory technology, which has the advantages of small size, low price, strong compatibility, and large storage capacity. CF card supports three interface modes, namely PCCard Memory Mode, PC Card I/O Mode, and True IDE Mode. Because True IDE Mode is not often used, the interface circuit is designed with PC Card Memory Mode and PC Card I/O Mode.
2.3 CPLD
CPLD (Complex Programmable Logic Device) is a more complex logic element than PLD [2]. It is a digital integrated circuit that users can construct logic functions according to their own needs. Its basic design method is to use the integrated development software platform, schematic diagram, hardware description language and other methods to generate the corresponding target file, and transfer the code to the target chip through the download cable ("in-system" programming) to realize the designed digital system.
The CPLD used in this paper is EPM7128SQL100-10 of Altera's MAX7000S series. It has 84 pins, 5 of which are used for ISP (IN System Programmable) download, which can be conveniently programmed "in-system". EPM7128SQL100-10 supports voltage operation and can be easily simulated, synthesized and downloaded using Altera's fourth-generation development platform quartus Ⅱ.
3 Hardware interface circuit design
The circuit diagram of the hardware interface circuit is shown in Figure 2. In this circuit, CPLD is used to implement the logic functions of some logic devices such as bidirectional buffers and NAND gates in general CF card interface circuits, making the interface circuit simpler, more stable, and faster, and different functions can be realized by modifying the program on site.
_CD1 and _CD2 in the CF card are status detection signals for whether the CF card is installed, and are grounded in the CF card. When the CF card is not installed, the output of _CD1 and _CD2 in the circuit is pulled high by the pull-up resistor; when the CF card is installed, _CD1 and _CD2 are grounded by the CF card and output low, and _CD1 and _CD2 are equivalent to the main switch of the CF card. In the actual interface circuit, _CD1 and _CD2 should be connected to a 10 kΩ pull-up resistor.
Programming CS4A of the chip select task register to 1 enables the multiplexed pins NCS4/CFCS, NCS5/CFCE1, and NCS6/CFCE2 of the EBI as CompactFlash signals CFCS, CFCE1, and CFCE2, and enables NOE/NRD/CFOE, NWR0/NEW/CFWE, NWR1/NBS1/CFIOR, NWR3/NBS3/CFIOW, and A25/CFRNW as Compact Flash signals CFOE, CFWE, CFIOR, CFIOW, and CFRNW. In this way, the external CF card can be accessed by accessing the address space reserved for NCS4. In the address space of NCS4, the current transfer address is used to distinguish the I/O mode, and the general storage mode is the flag storage mode. A23 of the transfer address bus is used to select the I/O mode. This CF card uses A22/REG to separate the general storage mode and the flag storage mode.
In I/O mode, the logic of CompactFlash drives the read and write signals of SMC on CFIOR and CFIOW signals, and CFOE and CFWE signals are invalid. Similarly, in general storage mode and flag storage mode, the logic drives SMC on CFOE and CFWE signals, and CFIOR and CFIOW signals are invalid. This logic is shown in Figure 3.
CFOE and CFWE are connected through the CPLD and the OE and WE of the CF card. This is the read and write enable of the CF card in Memory Mode.
CFIOE and CFIOW are the enable of I/O Mode. Except for the enable signal, other signals are the same for both modes.
The CFCE1 and CFCE2 signals enable the data bus of the CF card to be accessed from the top or bottom. For details, see Table 1. Odd byte access is only possible when the SMC on the NCS4 pin is configured to drive 8-bit memory. The chip select register in the NCS4 address space must be set as shown in Table 1.
When _CD1 and _CD2 are low level, the lower 11 bits A［10∶0］ of the CPU address bus are connected to the address bus A［10∶0］ of the CF card, and the lower 16 bits D［15∶0］ of the CPU data bus are connected to the address bus D［15∶0］ of the CF card. The A25/CFRNW signal of the CPU is the direction of the data flow, and the NCS4/CFCS signal is the transmission enable of the data bus. For details, please refer to Table 2.
CPU is a high-speed device, CF card is a low-speed device. When CPU transmits data to CF card, data loss may occur due to slow receiving speed. Therefore, _WAIT signal is needed to delay CPU transmission, so that the CPU transmission timing can match the CF card receiving timing, so that data transmission is correct. In the actual circuit, the CF card's _WAIT signal controls the CPU's NWAIT signal through CPLD, and _WAIT needs to be connected to a 10 kΩ pull-up resistor. RDY/BSY is the working status signal of CF card. When RDY/BSY is 1, CF card is ready to receive new data; when RDY/BSY is 0, CF card is receiving data, and this signal also needs to be connected to a 10 kΩ pull-up resistor. The reset RESET signal of CF card is also generated by inverting the system's reset nRESET signal in CPLD to keep synchronization with the system's reset signal.
4 CPLD Program Development
The CPLD program is written in Verilog HDL language under quartus Ⅱ. After the program is compiled, it is downloaded to the CPLD for solidification. The circuit board and the CF card are connected, and the data is read and written to the CF card. The test results show that the data transmission is correct and the transmission rate is higher.
5 Conclusion
This paper focuses on how to use CPLD to connect the ARM-based embedded system with the CF card. The CPLD used not only simplifies the interface circuit, making it suitable for field programming, but also improves the interface circuit. It is suitable for generating various complex combinational logic and sequential logic. The correctness of this storage technology has been verified on the circuit board, and it provides an effective solution for CF card storage of ARM-based embedded systems.
|
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
