Three-stage state machine description and template

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Three-stage state machine description and template [Copy link]

The state of a sequential circuit is a set of state variables, and the values of these state variables at any time contain all the historical information that must be considered to determine the future behavior of the circuit. The state machine is coded in VerilogHDL language, and it is recommended to be divided into three always segments. When describing the state machine output of FSM in three-segment modeling, you only need to specify the case sensitivity table as the next state register, and then directly describe the output of the state in the case branch of each next state without considering the state transition condition. Although the code structure of the three-segment description method is a bit complicated, the advantage is that it enables FSM to achieve synchronous register output, eliminates the hidden dangers of instability and glitches of combinational logic output, and is more conducive to timing path grouping. Generally speaking, it has better synthesis and layout and routing effects on programmable logic devices such as FPGA/CPLD. The examples are as follows: //The first process, the synchronous timing always module, formats the description of the migration of the next-state register to the current-state register always (posedge clk or negedge rst_n) //Asynchronous reset if (!rst_n) current_state <= IDLE; else current_state <= next_state; //Note that non-blocking assignment is used //The second process, the combinational logic always module, describes the state transfer condition judgment always @ (current_state) //Level trigger begin next_state = x; //To initialize so that the system can enter the correct state after reset case(current_state) S1: if(...) next_state = S2; //Blocking assignment ... endcase end //The third process, synchronization timing always module, format description of the next state register output always @ (posedge clk or negedge rst_n) ...//Initialization case(next_state) S1: out1 <= 1'b1; //Note that it is non-blocking logic S2: out2 <= 1'b1; default:... //The function of default is to avoid the synthesis tool from synthesizing latches endcase end The difference between a two-stage finite state machine and a three-stage finite state machine FSM separates the timing part (state transfer part) and the combination part (judging the state transfer condition and generating output) into two always statements, which is a two-stage finite state machine. Separate the judgment of the state transfer condition and the generation of input in the combination part to form a three-stage finite state machine. Difference: The two-stage method is applicable when the combinational logic is particularly complex, but it should be noted that a trigger should be added at the end to eliminate the burrs generated by the combinational logic on the output. The three-stage method does not have this problem because the third always will generate a trigger. Things to note when designing: 1. Coding principles. Binary and gray-code are suitable for situations where there are fewer trigger resources and rich combinational circuit resources (CPLD). For FPGA, one-hot code is suitable. This not only makes full use of the rich trigger resources of FPGA, but also because only one bit needs to be compared, the speed is fast and the combinational circuit is simple. 2. FSM initialization problem: GSR (Gobal Set/Reset) only clears all regs and on-chip RAM when power is turned on, and does not guarantee that the FSM can enter the initialization state. To use GSR, the solution is to use one-hot code with zero idle, that is, the initial state code is all zero. Asynchronous reset rst can be applied 3. FSM output can be applied to task 4 It is best to add default to the case in FSM, and the default state can be set to the initial state 5. Pay special attention: The judgment condition in the second paragraph of always (combination part, assignment with =) must include all situations! You can use else to ensure complete inclusion. 6 In the second paragraph of always, the combinational logic level must be maintained for more than one clock, pay attention when simulating.