Mingdeyang FPGA Series Course Phase 1 Chapter 2 FPGA Design Process

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Mingdeyang FPGA Series Course Phase 1 Chapter 2 FPGA Design Process [Copy link]

FPGA design process is the process of developing FPGA chips using EDA development software and programming tools. The typical FPGA development process is generally shown in the figure below, including function definition/device selection, design input, function simulation, comprehensive optimization, post-synthesis simulation, implementation, post-wiring simulation, board-level simulation, and chip programming and debugging.

Section 1: Function Definition/Device Selection

Before starting an FPGA design project, there must be a definition of system functions and a division of modules. In addition, according to the task requirements, such as the system's functions and complexity, the working speed and the device's own resources, cost, and the routability of the connection must be weighed to select the appropriate design solution and the appropriate device type. Generally, a top-down design method is adopted to divide the system into several basic units, and then each basic unit is divided into the basic units of the next level, and this is continued until the EDA component library can be used directly.

Section 2: Design Input

Design input is the process of expressing the designed system or circuit in a certain form required by the development software and inputting it into the EDA tool. Commonly used methods include hardware description language (HDL) and schematic input methods. Schematic input is the most direct description method. It was widely used in the early stage of programmable chip development. It calls the required devices from the component library and draws the schematic diagram. Although this method is intuitive and easy to simulate, it is inefficient and difficult to maintain, which is not conducive to module construction and reuse. The more important disadvantage is poor portability. When the chip is upgraded, all schematics need to be modified. At present, the most widely used in actual development is the HDL language input method, which uses text description design and can be divided into ordinary HDL and behavioral HDL. Ordinary HDLs include ABEL, CUR, etc., which support expressions such as logic equations, truth tables and state machines, and are mainly used for simple small designs. In medium and large projects, behavioral HDL is mainly used, and its mainstream languages are Verilog HDL and VHDL. Both languages are standards of the Institute of Electrical and Electronics Engineers (IEEE) of the United States. Their common outstanding features are: the language is independent of chip technology, conducive to top-down design, easy to divide and transplant modules, good portability, strong logic description and simulation functions, and high input efficiency. In addition to the IEEE standard language, there are also manufacturers' own languages. You can also use a mixed design method with HDL as the main and schematic diagram as the auxiliary to give full play to the respective characteristics of the two.

Section 3: Functional Simulation

Functional simulation, also known as pre-simulation, is to verify the logical function of the circuit designed by the user before compilation. At this time, the simulation has no delay information and only tests the preliminary functions. Before simulation, you must first use a waveform editor and HDL to create waveform files and test vectors (that is, combine the input signals of interest into a sequence). The simulation results will generate report files and output signal waveforms, from which you can observe the changes in the signals of each node. If an error is found, return to the design to modify the logic design. Commonly used tools include ModelSim from Model Tech, VCS from Sysnopsys, NC-Verilog and NC-VHDL from Cadence.

Section 4: Synthesis Optimization

Synthesis is the conversion of a higher level of abstraction into a lower level. Synthesis optimization optimizes the generated logic connections according to the goals and requirements, flattens the hierarchical design, and provides implementation for FPGA layout and routing software. At the current level, synthesis optimization refers to compiling the design input into a logic connection netlist composed of basic logic units such as AND gates, OR gates, NOT gates, RAMs, and flip-flops, rather than a real gate-level circuit. The actual gate-level circuit needs to be generated by utilizing the layout and routing function of the FPGA manufacturer according to the standard gate-level structure netlist generated after synthesis. In order to be converted into a standard gate-level structure netlist, the writing of the HDL program must conform to the style required by the specific synthesizer. Since the synthesis of gate-level structure and RTL-level HDL programs is a very mature technology, all synthesizers can support this level of synthesis. Commonly used synthesis tools include Synplicity's Synplify/Synplify Pro software and the synthesis development tools launched by various FPGA manufacturers.

5 Section 5: Post-synthesis simulation

Post-synthesis simulation checks whether the synthesis result is consistent with the original design. During simulation, the standard delay file generated by synthesis is annotated back into the synthesis simulation model to estimate the impact of gate delay. However, this step cannot estimate line delay, so there is still a certain gap between it and the actual situation after wiring, and it is not very accurate. The current synthesis tools are relatively mature, and this step can be omitted for general designs. However, if it is found that the circuit structure does not match the design intent after layout and wiring, it is necessary to go back to the post-synthesis simulation to confirm the problem. The software tools introduced in functional simulation generally support post-synthesis simulation.

Chapter 6 Layout and Routing

Layout and routing can be understood as using the implementation tool to map the logic to the resources of the target device structure, determine the best layout of the logic, select the routing channel that links the logic with the input and output functions for connection, and generate corresponding files (such as configuration files and related reports). Implementation is to configure the synthesized logic netlist to a specific FPGA chip, and layout and routing is the most important process. Layout rationally configures the hardware primitives and underlying units in the logic netlist to the inherent hardware structure inside the chip, and often needs to choose between speed optimization and area optimization. Routing uses various connection resources inside the chip to reasonably and correctly connect various components based on the topological structure of the layout. At present, the structure of FPGA is very complex, especially when there are timing constraints, it is necessary to use a timing-driven engine for layout and routing. After routing, the software tool will automatically generate a report to provide information about the usage of various resources in the design. Since only FPGA chip manufacturers know the chip structure best, layout and routing must use the tools provided by chip developers.

7Section 7: Timing Simulation

Timing simulation, also known as post-simulation, refers to the reverse annotation of the delay information of layout and routing into the design netlist to detect whether there is a timing violation (i.e., failure to meet the timing constraints or the inherent timing rules of the device, such as setup time, hold time, etc.). Timing simulation contains the most complete and accurate delay information, which can better reflect the actual working conditions of the chip. Since the internal delays of different chips are different, different layout and routing schemes also have different effects on the delay. Therefore, after layout and routing, it is very necessary to perform timing simulation on the system and each module, analyze the timing relationship, estimate the system performance, and check and eliminate competition risks. The software tools introduced in functional simulation generally support post-synthesis simulation.

Section 8: Board-level simulation and verification

Board-level simulation is mainly used in high-speed circuit design to analyze the signal integrity, electromagnetic interference and other characteristics of high-speed systems. Generally, third-party tools are used for simulation and verification.

Section 9: Chip Programming and Debugging

The last step of the design is chip programming and debugging. Chip programming refers to generating the data file used (bitstream generation), and then downloading the programming data to the FPGA chip. Among them, chip programming needs to meet certain conditions, such as programming voltage, programming timing and programming algorithm. Logic Analyzer (LA) is the main debugging tool for FPGA design, but it needs to lead out a large number of test pins, and LA is expensive. At present, mainstream FPGA chip manufacturers have provided embedded online logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII, and SignalProb) to solve the above contradictions. They only need to occupy a small amount of logic resources on the chip and have high practical value.

This book introduces the use of SIGNALTAP tools.

This content is originally created by EEWORLD forum user guyu_1. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source Board-level simulation is mainly used in high-speed circuit design to analyze the signal integrity, electromagnetic interference and other characteristics of high-speed systems. It is generally simulated and verified by third-party tools. Section 9: Chip Programming and Debugging The last step of the design is chip programming and debugging. Chip programming refers to generating the data file used (bitstream generation file), and then downloading the programming data to the FPGA chip. Among them, chip programming needs to meet certain conditions, such as programming voltage, programming timing and programming algorithm. Logic Analyzer (Logic Analyzer (LA) is the main debugging tool for FPGA design, but it needs to lead out a large number of test pins and LA is expensive. At present, mainstream FPGA chip manufacturers have provided embedded online logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII, and SignalProb) to solve the above contradictions. They only need to occupy a small amount of logic resources on the chip and have high practical value.

This book introduces the use of SIGNALTAP tools.

This content is originally created by EEWORLD forum user guyu_1. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source Board-level simulation is mainly used in high-speed circuit design to analyze the signal integrity, electromagnetic interference and other characteristics of high-speed systems. It is generally simulated and verified by third-party tools. Section 9: Chip Programming and Debugging The last step of the design is chip programming and debugging. Chip programming refers to generating the data file used (bitstream generation file), and then downloading the programming data to the FPGA chip. Among them, chip programming needs to meet certain conditions, such as programming voltage, programming timing and programming algorithm. Logic Analyzer (Logic Analyzer (LA) is the main debugging tool for FPGA design, but it needs to lead out a large number of test pins and LA is expensive. At present, mainstream FPGA chip manufacturers have provided embedded online logic analyzers (such as ChipScope in Xilinx ISE, SignalTapII in Altera QuartusII, and SignalProb) to solve the above contradictions. They only need to occupy a small amount of logic resources on the chip and have high practical value.

This book introduces the use of SIGNALTAP tools.

This content is originally created by EEWORLD forum user guyu_1. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source