TIDA-00961 FAQ for GaN-based High Efficiency 1.6kW CrM Totem Pole PFC Reference Design
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Author: TI engineers Aki Li, Rayna Wang High-frequency critical mode (CrM) totem-pole power factor correction (PFC) is an easy way to design high-density power solutions using GaN. The TIDA-00961 reference design uses TI’s 600V GaN power stage, the LMG3410, and TI’s Piccolo F280049 controller. The power stage size is 65 x 40 x 40mm, and the power density is greater than 250W/inch3; the efficiency can reach 98.7% at 230V AC input and full load; the power factor is >0.99, and the input current THD is small. This design is suitable for a variety of space-limited applications, such as servers, telecommunications, and industrial power supplies. At the same time, the hardware design meets the requirements of conducted emissions, surges, and EFT, which can help engineers achieve 80+ Titanium specifications. TIDA-00961 provides a set of cutting-edge solutions for the industry. This FAQ aims to solve the common problems encountered by many engineers in the process of learning this reference design. 1. How to obtain the control program of TIDA-00961? All the information (including schematics and programs) of TIDA-00961 are open and can be obtained in DigitalPower SDK. The program file location is: C:\ti\c2000\查看详情design tools, etc. (powerSUITEdesign tools, etc. 102)]Download link) 2. The design power of the reference solution is 1.6kW. If you want to apply it to higher power occasions, what suggestions do you have? The full load design power of TIDA-00961 is 1.6kW (high line 230V) and 1.2kW (low line 110V), which is mainly considered in consideration of the design power of the GaN half-bridge power board. At the same time, since the peak current in the CrM control mode is twice the average current, it is recommended that a GaN The design power of the half-bridge power board is 1kW, so this reference design can actually work at a full load power of 2kW (has passed actual testing). If you want to apply this solution to higher power occasions, such as 3kW, you can refer to the following three implementation methods: 1) Use multi-tube parallel connection, such as double-tube parallel connection to reduce the conduction loss introduced by GaN in the power circuit to half of the original, thereby increasing the power on the basis of unchanged topology and control method; 2) Increase the number of interleaved parallel phases, for example, upgrade the original two-phase interleaved topology to a three-phase interleaved parallel topology, and at the same time, change the phase shift angle of the other two phases from 1800 to 1200 and 2400 in terms of control.85)]3) The GaN used in the current solution is LMG3410(Rdson=70mΩ). The next generation of GaN Polaris will be launched soon (expected in the first half of 2019, and you can contact the TI sales team for sample application). It has lower on-resistance (Rdson=50mΩ), a single tube can bear more power, and is compatible with the LMG3410 pins, and the hardware topology and software control do not need to be changed. Therefore, directly using Polaris is the easiest way to increase system power. 3. PFC reference design that also uses GaN to achieve high efficiency PMP20873 is based on CCM mode. What are the considerations for adopting CrM control in the solution? TI GaN LMG3410 avoids the reverse recovery problem of Si MOSFET, so it can be used to realize the CCM working mode of totem pole topology, as shown in the reference design PMP26873, but it is noted that the switching frequency of this design is 100kHz. If you want to increase the power density by further increasing the switching frequency, the CCM working mode will encounter bottlenecks. Although GaN has advantages over Si MOSFET in switching loss performance, specifically (see Figure 1), its turn-on loss is higher than the turn-off loss during hard switching. Once the switching frequency is increased to several hundred or MHz, the proportion of switching loss will be greatly increased. Therefore, the use of CrM mode to achieve zero voltage turn-on (ZVS) provides the possibility of higher switching frequency and higher power density. 85)]查看详情 Figure 1 4. What is the reason for the reference design to adopt a two-phase interleaved topology? 1) By interleaving two phases in parallel, the power level of the system can be increased to twice the original level. 2) Compared with the two-phase interleaved parallel, the single-phase circuit of the same power has a larger effective current in CRM mode. Since the peak current in the switching cycle is twice the average current, the current fluctuation is large, which will inevitably increase the conduction loss of the line and the device. By staggered parallel connection, the ripples of each phase input current or each phase output current cancel each other out, which greatly improves the THD performance, reduces the requirements for the size of the input differential mode filter and the output capacitor, and reduces the loss of the input filter and the output capacitor. 5. How to understand Phase shedding? Phase shedding is used to improve system efficiency. When the load becomes smaller (less than the set current threshold), Phase shedding is enabled to close the second phase, thereby improving the efficiency of the system under light load. It is worth noting that the moment when Phase shedding needs to be enabled occurs at the moment when the voltage crosses the zero point. At this time, the energy in the loop is the smallest, thereby avoiding the current overshoot or oscillation caused by Phase shedding. 6. In the program, when the load increases and the second phase is added, why is there a gv_out = gv_out*(0.6) process? The 0.6 coefficient process is to prevent potential voltage overshoot problems. Under light load conditions, only one phase is working. At this time, if the load increases to exceed the set threshold, the second phase needs to be enabled immediately. If the duty cycle of the second phase is consistent with the duty cycle of the first phase at the previous moment, it is equivalent to generating twice the energy output. Since the load is only slightly increased at this time, it will cause a large output voltage overshoot. Therefore, in theory, the coefficient in the formula should be 0.5, but considering that the actual load is still increasing, it is more appropriate to use a coefficient of 0.6. 7. The reference design has a PWM frequency of up to 1.2MHz. What is the main guarantee?85)]3) Wide bandgap semiconductor device GaN makes MHz switching frequency possible. TI's LMG3410 built-in driver minimizes the impact of loop parasitic inductance and can still maintain very low loss under high-frequency switching. 4) To achieve accurate and efficient control of the system under such high-frequency switching, it relies on the excellent computing power of TI's new generation C2000 MCU TMS320F28004x. The main frequency of 100MHz, in addition to the floating-point unit (FPU), has added a trigonometric function unit (TMU). Through hardware acceleration, the speed of complex operations such as division, sine, cosine and root mean square is greatly accelerated, thereby ensuring the implementation of algorithms such as high-frequency interrupt inner loop control and ZVS control. At the same time, the Type 4 ePWM of F28004x can achieve high-precision control of duty cycle, period, and dead time, maintaining control precision and accuracy under high-frequency switching. 8. How to ensure the consistency of two-phase interleaving control without error under high-frequency operation? This reference design adopts the new generation of C2000 MCU TMS320F28004x, the latest Type 4 ePWM introduces one-time loading and global loading functions, ensuring that registers such as duty cycle and phase are updated simultaneously based on the same set event, which can avoid potential phase control errors in multi-phase control applications. 9. Is there any challenge in EMI when the switching frequency reaches MHz? Compared with the traditional PFC application under CCM mode, the switching frequency of this reference design reaches up to MHz, and two-phase interleaved parallel control is adopted. In theory, the size of the differential mode filter can be greatly reduced, but it is also noted that the CrM mode is variable frequency control, and the requirements for filter design will be correspondingly increased; on the other hand, the GaN LMG3410 can flexibly adjust the dv/dt by adjusting the size of the external resistor, which helps to improve the EMI problem. At present, the development board of this reference design is planning to deliver EMI test, and we will update the test results as soon as possible. 10. The controlISR interrupt frequency in the program is 50kHz, which includes a large number of calculations. How much time is left after the interrupt runs? The controlISR interrupt is mainly used for current loop control and phase-locked loop calculation. Through actual tests, the required running time of the interrupt is 12.4μs, and the CPU bandwidth occupancy is about 60%, as shown in Figure 2. In addition, the control program also includes two other interrupts: tenKHzISR with a frequency of 10kHz, which is used for voltage loop and phase shedding processing, and the required running time is 20.8μs; pwmISR with a frequency of 1/3 of the PWM frequency, which is used for ZVS adjustment and phase shift synchronization control, and the required running time is 2.04μs. It can be seen that thanks to the excellent computing power of F28004x, the CPU bandwidth occupancy rate of this control system is relatively low, and it can still provide sufficient margin for additional user functions. Figure 2 System interruption time 11. There is no OCP protection circuit in the schematic diagram. How to implement this protection function? 1) This solution does not require an external OCP circuit. By sampling the input current, the window comparator (CMPSS) on the F28004x chip is directly used to simultaneously implement OCP for the positive and negative half cycles of the input current. It does not require CPU judgment and processing, and can achieve a fast protection capability of about 60ns through hardware. 2) In addition, TI GaN LMG3410 integrates OCP, OTP and other protection functions. If the power circuit has overcurrent, LMG3410 can immediately shut down to achieve protection. 12. The boost inductor of PFC in the schematic diagram is 15uH. How to avoid the current spike when the input voltage passes through zero? 85)]The boost inductor in the scheme is small, and even a small voltage will cause rapid current changes, especially when the voltage passes through zero, current spikes are prone to occur. Therefore, this design uses soft start control at the moment when the input voltage passes through zero. By judging the size of the input voltage, the state machine is used to control the switching timing of GaN and MOSFET, eliminating the current spike at the zero point and further improving the current THD. For the specific principle of soft start, please refer to Section 2.4.4 in the TIDM-1007 reference design description.13. How to determine the on and off time of the power tube in a switching cycle? The control mode of this system is based on the constant on-time mode. The control system consists of an output voltage outer loop and an input current inner loop. The on time Ton is mainly determined by the voltage loop. At the same time, the current inner loop is introduced to fine-tune and optimize the THD of the input current. The off time Toff is obtained according to the volt-second balance principle. 14. Which parts of the hardware circuit are valid parts of the ZVS detection circuit? Answer: We have used a variety of ways to implement ZVS during the design process. Currently, the valid ZVS detection signals are ZVS1_2 and ZVS2_2. The circuits used to generate ZCD_OUTPUT1/2, ZVS1/2 and CROSSOVER signals are redundant and no longer used. [size= 14px] Figure 3 Redundant circuit 15. How is ZVS implemented in the reference design? The reference design implements ZVS through two mechanisms: adjusting the dead time before turning on the main working tube and adjusting the conduction time of the freewheeling tube, as follows: 1) Adjust the dead time before turning on the main working tube Through circuit analysis, it can be obtained that when the freewheeling tube is turned off and before the main working tube is turned on, the Vds voltage on the main working tube satisfies the following requirements: 85)]查看详情 When the input and output voltages meet Vin<0.5Vout, when the main switch is turned off, Vds can reach 0 through the resonance of the inductor and the parasitic capacitance of the switch, so that Naturally achieve zero voltage turn-on ZVS. When Vin>0.5Vout, Vds cannot reach 0 through resonance. To achieve full range ZVS, additional control algorithms need to be added. The specific idea is to provide a period of time after the inductor current drops to 0. The negative inductor current Io during the (dead time) injects energy into the resonant circuit, allowing Vds to reach 0. 85, 85, 85)]When Vds drops to 0, there is [color=rgb (85, 85, 85)] 查看详情 Further calculate the dead time, In addition, when Vin<0.5Vout, the corresponding dead time is [ color=rgb(85, 85, 85)] 查看详情 2) Adjust the on-time of the freewheeling tube toff_calc Through the external ZVS detection circuit, which is used to detect the slope (dv/dt) of Vds, ZVS1_2 is generated as the input signal of the window comparator (CMPSS) on the F28004x chip. If a large ZVS1_2 is generated when the main working tube is turned on, it is judged through CMPSS that ZVS is not achieved at this time (zvs_lost = 1), so it is necessary to increase the conduction time toff_calc of the freewheeling tube in the next switching cycle; if it is judged that ZVS is achieved at this time, the conduction time of the freewheeling tube is reduced in the next switching cycle to avoid introducing too much negative current to affect the system efficiency. Therefore, this is a dynamic adjustment mechanism. In addition, when the program calculates toff_calc, for the working condition of Vin>0.5Vout, toff_calc also adds a delay time that is positively correlated with the input voltage based on the volt-second balance calculation result. For details, see the calculation of acSine_diff. 16. Is the dead time from the main working tube being turned off to the freewheeling tube being turned on fixed? The dead time corresponds to the resonance time of the parasitic capacitance of the switch tube and the boost inductor. In traditional analog control, a fixed dead time setting is generally used. However, within an input voltage AC cycle, the resonance time is variable. Therefore, too long or too short dead time is not conducive to improving efficiency, and it is easy to cause oscillation problems caused by inappropriate switching timing. This design adopts adaptive dead time control, and dead time is used in each switching cycle, thereby further improving system efficiency. 17. Can the system achieve ZVS in the full range? Answer: In the currently updated program, the operating condition for full-range ZVS control is: Vin effective value is less than 210V. When Vin effective value is greater than 210V, the conduction time of the freewheeling tube is not adjusted according to ZVS detection (ZVS extension). The current code is used for V2 version hardware circuit. In the future, the code will be optimized so that ZVS extension can work above 210V on V3 version circuit. 18. How to understand SPLL_1PH_SOGI_FLL_run(&spll3,ac_vol_sensed) and what is the purpose of the phase-locked loop? SPLL_1PH_SOGI_FLL_run is one of the official library functions of C2000. You can learn more about it through DigitalPower SDK. For specific usage and principles, please refer to the document "Digital Power Library USER'S GUIDE", file location C:\ti\c2000\C2000Ware_DigitalPower_SDK_1_01_00_00\docs. In this program, the phase-locked loop performs frequency and phase detection on the input voltage. The purpose is to: 1) determine the switching time of the positive and negative half-cycle open state; 2) perform soft-start processing on the switch signal when the voltage passes through zero point, so that the current at the zero point transitions smoothly to avoid the generation of current glitches; 85)]3) The sine value corresponding to the voltage phase is used to calculate the current given value of the current loop (ac_cur_ref_inst = ac_cur_ref*acSine, ac_cur_ref is the output of the voltage loop) for accurate tracking of the current loop; 19. In the program, the statement that controls the current loop is gi_out=DCL_runPI_C1(&gi, ac_cur_ref_inst), ac_cur_sensed), where ac_cur_ref is the output of the voltage loop. This control program integrates the Software Frequency Response Analyzer (SFRA) function. Engineers can directly use this program to enable the SFRA function to obtain the loop bandwidth and other parameters of the system online without adding any hardware equipment. Once enabled SFRAfunction, SFRA_F_INJECT(ac_cur_ref_inst) represents the small signal interference with a specific frequency superimposed on ac_cur_ref_inst. It is worth noting that the SFRA function is a tool that serves the project development stage. Once the system parameters are debugged, the corresponding SFRA embedded code can be removed to release the bandwidth occupied by it. For details, see the specific instructions for using SFRA. 20. Why does the test result in the manual show that the THD value changes when the system is working near Pout = 800W (Vin = 230V)? 102)]查看详情 Figure 4 THD test results Due to the change from phase shedding to 2nd phase on, the load value of each phase after addition is reduced to half of the original single-phase operation. Since the THD at low load is worse than that at high load, the THD value will suddenly increase when the second phase is turned on.
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