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The problem with ETH_RESET [Copy link]

First, here are the pictures: I designed an Ethernet circuit based on the STM32F767 development board. I don’t know how to deal with the ETH_RESET pin. I can’t understand the schematic. Can an expert explain it to me? Thank you!


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LAN8720A seems to be reset at a low level, so under normal circumstances, P7 output should be set low, and after the inversion of transistor Q1, ETH_RESET is always at a high level. When reset is required, P7 is set high for a short time to form a low-level reset signal on ETH_RESET.  Details Published on 2018-11-2 09:52
Personal signature为江山踏坏了乌骓马,为社稷拉断了宝雕弓。
 

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When the system finds that the network port chip LAN8720A is not working properly, such as being unable to connect to the Internet for a long time, this pin can be used to force the LAN8720A to reset and restart.
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LAN8720A seems to be reset at a low level, so under normal circumstances, P7 output should be set low, and after the inversion of transistor Q1, ETH_RESET is always at a high level. When reset is required, P7 is set high for a short time to form a low-level reset signal on ETH_RESET.
This post is from stm32/stm8

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Thanks!  Details Published on 2018-11-2 10:24

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topwon posted on 2018-11-2 09:52 LAN8720A seems to be a low-level reset, so under normal circumstances, the P7 output should be set low, and after the inversion processing of the transistor Q1, ETH_RESE ...
Thank you!
This post is from stm32/stm8
 
Personal signature为江山踏坏了乌骓马,为社稷拉断了宝雕弓。
 
 

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