Behavioral modeling sequential logic circuit (two-input AND gate) source code and test code

zxopenljx

Behavioral modeling sequential logic circuit (two-input AND gate) source code and test code [Copy link]

Source code:
module and_gate1(clk, a, b, s);

input clk;
input a;
input b;

output reg s;

//Behavioral modeling sequential logic circuit (two-input AND gate)
always @ (posedge clk) //Rising edge triggered
begin
s <= a & b;
end
endmodule

test code:
`timescale 1ns/1ps
module and_gate1_tb;

reg clk;
reg a;
reg b;

wire s;

and_gate1 and_gate1a(
.clk(clk),
.a(a),
.b(b),
.s(s)
);

initial
begin
clk = 0;
a = 0; b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
#100 $stop;
end

always #10 clk = ~clk;
endmodule

zxopenljx · Published on 2019-12-22 22:54

zxopenljx

Behavioral modeling sequential logic circuit (two-input AND gate) source code and test code

zxopenljx

Behavioral modeling sequential logic circuit (two-input AND gate) source code and test code

雷北城

Thanks for sharing, I learned a lot

Behavioral modeling sequential logic circuit (two-input AND gate) source code and test code [Copy link]

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