DSP56858 General Description
• 120 MIPS at 120MHz
• 40K x 16-bit Program SRAM
• 24K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M data
memory
• Chip Select Logic for glue-less interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Two (2) Enhanced Synchronous Serial Interfaces
(ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• Serial Port Interface (SPI)
• 8-bit Parallel Host Interface
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of -Day (TOD)
• 144 LQFP and 144 MAPBGA packages
• Up to 47 GPIO
6
V
DDIO
12
V
DD
8
V
SSIO
14
V
SS
V
DDA
8
V
SSA
2
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
16-Bit
56800E Core
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
40,960 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System Bus
Control
DMA
6 channel
Core CLK
IPBus Bridge (IPBB)
IPWDB
Decoding
Peripherals
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-A3
Bus Control
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
2 SCI ESSI0
or
or
GPIOE GPIOC
IPRDB
IPAB
DMA Requests
IPBus CLK
POR
CLKO
3
MODE A-C or
GPIOH0-H2
System
COP/TOD CLK Integration
Module
RSTO
RESET
ESSI1
or
GPIOD
Quad
Timer
or
GPIOG
4
SPI
Host
Interrupt
or
Interface Controller
GPIOF
or
GPIOB
4
16
IRQA
IRQB
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
4
6
6
56858 Block Diagram
56858 Technical Data, Rev. 6
Freescale Semiconductor
3
Part 1 Overview
1.1 56858 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C-Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
On-Chip Memory
— 40K
×
16-bit Program RAM
— 24K
×
16-bit Data RAM
— 1K
×
16-bit Boot ROM
•
Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program or 8M data memory (using chip selects)
— Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3
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56858 Peripheral Circuit Features
General Purpose 16-bit Quad Timer*
Two Serial Communication Interfaces (SCI)*
Serial Peripheral Interface (SPI) Port*
Two (2) Enhanced Synchronous Serial Interface (ESSI) modules*
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
56858 Technical Data, Rev. 6
4
Freescale Semiconductor
56858 Description
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Six (6) independent channels of DMA
8-bit Parallel Host Interface*
Time-of-Day (TOD)
Up to 47 GPIO
* Each peripheral I/O can be used alternately as a GPIO if not needed
1.1.4
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Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
Wait and Stop modes available
1.2 56858 Description
The 56858 is a member of the 56800E core-based family of controllers. This device combines the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals on a single chip to create an extremely cost-effective solution. The low cost,
flexibility, and compact program code make this device well-suited for many applications. The 56858
includes peripherals that are especially useful for teledatacom devices; Internet appliances; portable
devices; TAD; voice recognition; hands-free devices; and general purpose applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of
optimized control applications.
The 56858 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56858 also provides two external
dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56858 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot
RAM. It also supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include an 8-bit Parallel
Host Interface, two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI),
two Serial Communications Interfaces (SCI), and one Quad Timer. The Host Interface, Quad Timer, SSI,
SPI, SCI I/O and four chip selects can be used as General Purpose Input/Outputs when its primary function
is not required.
1.3 State of the Art Development Environment
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Processor Expert
TM
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
56858 Technical Data, Rev. 6
Freescale Semiconductor
5
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