MPC8536AVTAVL datasheet, PDF - EEWORLD Datasheet

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MPC8536AVTAVL: DescriptionMicroprocessors - MPU 8536 COMMERCIAL 1500; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，126 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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Microprocessors - MPU 8536 COMMERCIAL 1500

MPC8536AVTAVL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	PGA
package instruction	29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, FCBPGA-783
Contacts	783
Reach Compliance Code	not_compliant
ECCN code	5A992
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
JESD-609 code	e2
length	29 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	783
Maximum operating temperature	90 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA783,28X28,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1,1.5/1.8,1.8/3.3 V
Certification status	Not Qualified
Maximum seat height	2.76 mm
speed	1500 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC8536EEC

Rev. 5, 09/2011

MPC8536E

MPC8536E PowerQUICC III

Integrated Processor

Hardware Specifications

• High-performance, 32-bit e500 core, scaling up to

1.5 GHz, that implements the Power Architecture®

technology

– 36-bit physical addressing

– Double-precision embedded floating point APU using

64-bit operands

– Embedded vector and scalar single-precision

floating-point APUs using 32- or 64-bit operands

– Memory management unit (MMU)

• Integrated L1/L2 cache

– L1 cache—32-Kbyte data and 32-Kbyte instruction

– L2 cache—512-Kbyte (8-way set associative)

• DDR2/DDR3 SDRAM memory controller with full ECC

support

– One 64-bit/32-bit data bus

– Up to 333-MHz clock (667-MHz data rate)

– Supporting up to 16 Gbytes of main memory

– Using ECC, detects and corrects all single-bit errors and

detects all double-bit errors and all errors within a nibble

– Invoke a level of system power management by

asserting MCKE SDRAM signal on-the-fly to put the

memory into a low-power sleep mode

– Both hardware and software options to support

battery-backed main memory

• Integrated security engine (SEC) optimized to process all

the algorithms associated with IPsec, IKE, SSL/TLS,

iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP.

– XOR engine for parity checking in RAID storage

applications

• Enhanced Serial peripheral interfaces (eSPI)

– Support boot capability from eSPI

• Two enhanced three-speed Ethernet controllers (eTSECs)

with SGMII support

– Three-speed support (10/100/1000 Mbps)

– Two IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and

IEEE Std 1588™-compatible controllers

MAPBGA–783

29 mm x 29 mm

•

– Support for various Ethernet physical interfaces: GMII,

TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII

– Support TCP/IP acceleration and QOS features

– MAC address recognition and RMON statistics support

– Support ARP parsing and generating wake-up events

based on the parsing results while in deep sleep mode

– Support accepting and storing packets while in deep

sleep mode

High-speed interfaces (multiplexed) supporting:

– Three PCI Express interfaces

– PCI Express 1.0a compatible

– One x8/x4/x2/x1 PCI Express interface

– Two x4/x2/x1 ports, or,

– One x4/x2/x1 port and Two x2/x1 ports

– Two SGMII interfaces

– Two Serial ATA (SATA) controllers support SATA I and

SATA I data rates

PCI 2.2 compatible PCI controller

Three universal serial bus (USB) dual-role controllers

comply with USB specification revision 2.0

133-MHz, 32-bit, enhanced local bus (eLBC) with memory

controller

Enhanced secured digital host controller (eSDHC) used for

SD/MMC card interface

– Support boot capability from eSDHC

Integrated four-channel DMA controller

Dual I

C and dual universal asynchronous

receiver/transmitter (DUART) support

Programmable interrupt controller (PIC)

Power management, low standby power

– Support Doze, Nap, Sleep, Jog, and Deep Sleep mode

– PMC wake on: LAN activity, USB connection or remote

wakeup, GPIO, internal timer, or external interrupt event

System performance monitor

IEEE Std 1149.1™-compatible, JTAG boundary scan

783-pin FC-PBGA package, 29 mm

29 mm

Table of Contents

Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3

1.1 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21

2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .32

2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2.10 Ethernet Management Interface Electrical Characteristics

2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .66

2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .75

2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .77

2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.17 I

C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .91

2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 114

3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.2 Power Supply Design and Sequencing . . . . . . . . . . . 114

3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 115

3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 115

3.5 SerDes

Block

Power

Supply

Decoupling

Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 116

3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 116

3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 116

3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 117

3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 118

3.11 Guidelines for High-Speed Interface Termination . . . 120

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.1 Part Numbers Fully Addressed by this Document. . . 122

4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.1 Package Parameters for the FC-PBGA . . . . . . . . . . . 123

5.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 124

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 125

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

MPC8536AVTAVL Related Products

	MPC8536AVTAVL	MPC8536EBVTANG
Description	Microprocessors - MPU 8536 COMMERCIAL 1500	Microprocessors - MPU 32-BIT 800MHz
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	PGA	PGA
package instruction	29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, FCBPGA-783	29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, FCBPGA-783
Contacts	783	783
Reach Compliance Code	not_compliant	not_compliant
ECCN code	5A992	5A002
Address bus width	32	32
bit size	32	32
boundary scan	YES	YES
maximum clock frequency	133 MHz	133 MHz
External data bus width	32	32
Format	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES
JESD-30 code	S-PBGA-B783	S-PBGA-B783
JESD-609 code	e2	e2
length	29 mm	29 mm
low power mode	YES	YES
Humidity sensitivity level	3	3
Number of terminals	783	783
Maximum operating temperature	90 °C	105 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA
Encapsulate equivalent code	BGA783,28X28,40	BGA783,28X28,40
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	260
power supply	1,1.5/1.8,1.8/3.3 V	1,1.5/1.8,1.8/3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.76 mm	2.76 mm
speed	1500 MHz	800 MHz
Maximum supply voltage	1.155 V	1.155 V
Minimum supply voltage	1.045 V	1.045 V
Nominal supply voltage	1.1 V	1.1 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal surface	TIN SILVER	Tin/Silver (Sn/Ag)
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40
width	29 mm	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR

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