Data Sheet
FEATURES
NatureVue Video Signal Processor with
Bitmap OSD, Dual HDMI Tx, and Encoder
ADV8005
Easy to use software tool for developing OSDs
HDMI transmitters
Dual 4k × 2k HDMI transmitters
Audio return channel (ARC) support
Dual audio insertion from TMDS Rx or from audio input pins
Support for serial audio using the S/PDIF audio pin
8-channel I
2
S audio inputs supporting up to 192 kHz
sample frequency
6-channel direct stream digital (DSD) audio inputs
Noise shaped video (NSV) 6-DAC video encoder
Six 12-bit NSV video DACs supporting SD, ED and HD video
Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant
Professional video features
Capability to output up to 36-bit TTL pixel data
Full color space converter on the output TTL pixel data
TTL video, audio, SPI, and interrupt pins disabled by default
Ability to synchronize output video to externally applied
reference sync signals
Video signal processor
Full 12-bit, 4:4:4 YCbCr (color space) internal processing
Motion adaptive deinterlacing with ultralow angle
interpolation
Multiple video processing paths with up to 3 simultaneous
video streams including picture-in-picture (PiP) support
Upscaling and downscaling to/from 4k × 2k
Aspect ratio conversion/panorama scaling
Cadence detection for the recovery of original frames from
film-based content
Dual video scalers enable simultaneous output of multiple
different resolutions
Sharpness and detail enhancement
Noise reduction for random, mosquito, and block noise
Frame rate converter (FRC)
Video metrics readback to enable correct phase and
frequency selection for graphics inputs
On-screen display (OSD)
Internally generated bitmap-based OSD allowing overlay
on one or more video outputs
Overlay on 3D and 4k × 2k video formats
Dedicated OSD scaler
Alpha blending of OSD data on video data
Disturbance free blending of OSD on either of 2 zones
Support for external OSD
APPLICATIONS
High end A/V receivers
Upconverting DVD players/recorders
Video conferencing and distribution
HDMI splitters
Video walls
FUNCTIONAL BLOCK DIAGRAM
ADV8005
60-BIT
TTL PORT
24-BIT/
36-BIT/
48-BIT
VIDEO
INPUT
36-BIT
VIDEO
OUTPUT
DDR2 INTERFACE
OSD BUILD
AND SCALE
LOW ANGLE
PROCESSING
CADENCE
DETECTION
MOTION
DETECTION
CUE
CORRECTION
DEINTERLACER
VIDEO PROCESSING
DETAIL
ENHANCE
NOISE
REDUCTION
ENHANCE
DUAL SCALER
AND
OSD BLEND
FRC
HDMI Tx1
HDMI
TTL DATA
HDMI Tx2
HDMI
HD VIDEO
DACs
HD VIDEO
SD VIDEO
DACs
SD VIDEO
SERIAL VIDEO
FOR EXAMPLE, ADV7850
OUTPUT
SERIAL
VIDEO
RECEIVER
12074-001
AUDIO INPUT
Figure 1.
Rev. 0
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ADV8005
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
ADV8005 Models ......................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
Electrical Characteristics ............................................................. 5
Analog Specifications ................................................................... 7
Data and I
2
C Timing Characteristics ......................................... 7
Absolute Maximum Ratings.......................................................... 17
ESD Caution ................................................................................ 17
Pin Configurations and Function Descriptions ......................... 18
Theory of Operation ...................................................................... 45
Video Input.................................................................................. 45
Data Sheet
Professional Configuration ....................................................... 45
External Sync mode ................................................................... 45
Flexible Digital Core .................................................................. 45
Video Signal Processor (VSP) ................................................... 45
On-Screen Display (OSD) ......................................................... 46
External DDR2 Memory ........................................................... 46
HDMI Transmitters ................................................................... 46
Video Encoder ............................................................................ 46
Typical Application Diagram .................................................... 47
Design Considerations................................................................... 48
Power-Up Sequence ................................................................... 48
Thermal Considerations............................................................ 48
Register Map Architecture ............................................................ 49
Outline Dimensions ....................................................................... 50
Ordering Guide .......................................................................... 50
REVISION HISTORY
6/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
Data Sheet
GENERAL DESCRIPTION
The
ADV8005
is a multiple input video signal processor that can
deinterlace and scale standard definition (SD), enhanced
definition (ED), or high definition (HD) video data to ultra HD
formats; generate a bitmap on-screen display (OSD); and output
the video with OSD overlaid on two High-Definition Multimedia
Interface (HDMI®) transmitters and a video encoder.
The 60-bit TTL video port can be used to input video to the
ADV8005
in a number of ways: using the 48-bit TTL pixel port,
using the 24-bit external OSD TTL pixel port, or from a device
with an HDMI transmitter such as the
ADV7850.
The
ADV8005
supports many of the formats outlined in the CEA-861-F and
VESA specifications, as well as several other widely used timing
formats.
The
ADV8005
features primary and secondary video scalers
that enable simultaneous output of multiple different resolutions.
The primary video scaler can upscale to 4k × 2k modes. The
secondary video scaler can upscale to 1080p or UXGA graphics.
4k × 2k downscaling is performed using the secondary video
scaler, leaving the primary video scaler available for other video
processing.
The
ADV8005
primary video scaler can perform high
performance, motion adaptive interlaced to progressive
conversion on SD and HD content. Additional functionality has
also been added to
ADV8005
to facilitate upscaling and
downscaling to VESA formats with pixel clock frequencies below
300 MHz.
Detail enhancement and image enhancing techniques such as
random, mosquito, and block noise reduction allow improved
final image quality. The frame rate converter of the
ADV8005
allows the conversion between common frame rates with support
to output two different frame rates simultaneously under certain
conditions.
The
ADV8005
can accept OSD information from an external OSD
source on one of its inputs, or it can internally generate a high
quality, bitmap-based OSD. The internal OSD is highly flexible
and allows the system designer to easily incorporate features
ADV8005
like scrolling text and animation in various color depths up to
24-bit true color.
Analog Devices, Inc., provides an OSD development tool (Blimp)
to assist in the design, debug, and emulation of the OSD prior
to integration with the system application. When the design is
complete, the OSD development tool automatically generates
code to which system application programming interfaces
(APIs) can be added before integration with the system
application and an OSD design resource, which must be
downloaded to an external SPI flash memory.
Video can be output from the
ADV8005
using one or both of the
HDMI transmitters and/or the six-DAC SD/HD video encoder.
The six 12-bit NSV® video DACs allow composite (CVBS),
S-Video (Y/C), and component (YPrPb) analog outputs in
standard, enhanced, and high definition video formats.
Oversampling of 216 MHz (SD and ED) and 297 MHz (HD)
removes the requirement for external output filtering. Rovi® and
non-Rovi variants of the
ADV8005
are available.
Both of the HDMI transmitters on the
ADV8005
support 4k × 2k
and all mandatory and many optional 3D video resolutions. Each
transmitter features an audio return channel receiver (ARC).
The
ADV8005
can receive up to eight channels of I
2
S, S/PDIF,
direct stream digital (DSD), and high bit rate (HBR) audio passed
from either the serial video Rx or from the externally available
audio input pins.
The
ADV8005
supports the I
2
C protocol for communication
with the system microcontroller.
ADV8005
MODELS
The
ADV8005
includes a number of models, each featuring
different capabilities; all are provided in the same 19 mm ×
19 mm, 425-ball CSP_BGA package (see Table 9).
Note that the functionality of the
ADV8005KBCZ-8A
is
described throughout this data sheet. Some sections are not
relevant to other models because not all of the blocks found in
the
ADV8005KBCZ-8A
are included in those models. Table 9
lists the functionality for each model.
Rev. 0 | Page 3 of 52
ADV8005
DDR_VREF
DDR_CAS
DDR_RAS
DDR_A[13:0]
DSD_CLK
DDR_CK
DDR_CK
DDR_BA[2:0]
DDR_CS
DDR_DQS[3:0]
DDR_WE
DDR_DQS[3:0]
MUXING
RX_0P
RX_0N
RX_1P
RX_1N
RX_2P
RX_2N
RX_CP
RX_CN
RX_HPD
RX_5V
Auto -
Position
Auto-Phase
OSD VIDEO
BLEND
COLOR SPACE
CONVERSION
UPDITHER
DDR_DQ[31:0]
DDR_DM[3:0]
AUD_IN[5:0]
SCLK
MCLK
DDR2 CONTROLLER INTERF ACE
HDCP AND EDID
UNCONTROLLER
AUDIO DATA CAPTURE
DDR2 INTERFACE
I
2
C
MASTER
DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA
HPD_TX1
HPD_TX2
HDCP
KEYS
RECEIVER
HDCP
ENCRYPTION
HDMI Tx
VIDEO DATA
CAPTURE
4:4:4
AND
COLOR SPACE
CONVERTER
4:2:2
TMDS
OUTPUTS
P[35:0]
VIDEO
ENHANCEMENT
DETAILED FUNCTIONAL BLOCK DIAGRAM
TX1_0+
TX1_0–
TX1_1+
TX1_1–
TX1_2+
TX1_2–
TX1_C+
TX1_C–
HDCP
ENCRYPTION
HDCP
KEYS
4:4:4
AND
COLOR SPACE
CONVERTER
4:2:2
HS
DE-INTERLACER
AND CADENCE
DETECTION
MOTION
DETECTION
RANDOM
NOISE
REDUCTION
SCALING AND
FRAME RATE
CONVERSION
VS
SCALER 1
OSD
GENERATION
PCLK
COLOR SPACE
CONVERSION
UPDITHER
DE
BITMAP OSD
CONTROLLER
OSD
SCALER
DIGITAL
VIDEO
CAPTURE
AND
FORMATTING
OSD_HS
LOW ANGLE
PROCESSING
HDMI Tx
VIDEO DATA
CAPTURE
COLOR SPACE
CONVERSION
UPDITHER
OSD_DE
OSD_CLK
OSD_IN[12]
CADENCE
DETECTION
CUE
CORRECTION
OSD VIDEO
CAPTURE
AND
FORMATTING
BLOCK
NOISE
REDUCTION
FRAME
RATE
CONVERTER
DETAIL
ENHANCE-
MENT
VIDEO MUXING
COLOR SPACE
CONVERSION
ED/HD
PROCESSOR
SD
PROCESSOR
MULTIPLEXER
INT0
INT1
INT2
POWER
SUPPLY
ARC PORT
16×/4× OVERSAMPLING FILTERS
2 × PLLs
12074-003
Figure 2. ADV8005KBCZ-8A Functional Block Diagram
MOSQUITO
NOISE
REDUCTION
Rev. 0 | Page 4 of 52
SCALER 2
TMDS
OUTPUTS
OSD_VS
TX2_0+
TX2_0–
TX2_1+
TX2_1–
TX2_2+
TX2_2–
TX2_C+
TX2_C–
PROGRAMMABLE
HDTV FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
ENCODER
12-BIT
DAC1
12-BIT
DAC2
OSD_IN[23:16]/
EXT_DIN[7:0],
OSD_IN[11:0]
DAC1
DAC2
12-BIT
DAC3
OSD_IN[15:13]/
VBI_x
SPI SLAVE
XTALN
XTALP
CLOCK
GENERATION
TO VBI
INSERTION
IN ENCODER
BLOCK
VIDEO PROCESSING AND OSD BLENDING
PROGRAMMABLE
LUMINANCE
FILTERS
I/O, OSD, ENCODER
VSP, HDMI Tx
REGISTER MAPS
SYNC
INSERTION
DAC3
12-BIT
DAC4
DAC4
PROGRAMMABLE
CHROMINANCE
FILTERS
SIN/COS
MODULA-
TION/COS
12-BIT
DAC5
12-BIT
DAC6
TOP LEVEL
CONTROL
HEAC
MASTER
TIMING
BLOCK
CONTROL
DAC5
DAC6
RESET
GENERATION
AND POWER
MANAGEMENT
SPI
SLAVE
SPI
MASTER
I
2
C SLAVE
VBI DATA SERVICE
INSERTION
SUBCARRIER
FREQ LOCK
REFERENCE
AND CABLE
DETECTION
SFL
CS1
CS2
SCL
PDN
SDA
SCK1
SCK2
VREF
ALSB
DVDD
ELPFx
RSETx
MISO1
MISO2
MOSI1
MOSI2
AVDDx
PVDDx
REF_VS
REF_HS
REF_CLK
RESET
CVDD1
COMPx
DVDD_IO
HEAC_2+
HEAC_1+
HEAC_2–
HEAC_1–
ARC1_OUT
ARC2_OUT
PVDD_DDR
DVDD_DDR
Data Sheet
Data Sheet
SPECIFICATIONS
ADV8005
Measured at DVDD = 1.746 V to 1.854 V, DVDD_DDR = 1.746 V to 1.854 V, PVDD1 = 1.746 V to 1.854 V, PVDD2 = 1.746 V to 1.854 V,
PVDD3 = 1.746 V to 1.854 V, PVDD5 = 1.789 V to 1.90 V, PVDD6 = 1.789 V to 1.90 V, PVDD_DDR = 1.746 V to 1.854 V, AVDD3 =
1.746 V to 1.854 V, AVDD4 = 1.746 V to 1.854 V, CVDD1 = 1.746 V to 1.854 V, AVDD1 = 3.20 V to 3.40 V, AVDD2 = 3.20 V to 3.40 V,
DVDD_IO = 3.20 V to 3.40 V, T
MIN
to T
MAX
= 0°C to 70°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity, +ve
1
Integral Nonlinearity, −ve
1
Differential Nonlinearity, +ve
2
Differential Nonlinearity, −ve
2
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Leakage Current
Symbol
Test Conditions/Comments
Min
Typ
12
0.389
−0.322
0.183
−0.208
0.7 ×
DVDD_IO
0.3 ×
DVDD_IO
±60
±60
±10
±60
13
3.4
0.8
±60
2.4
0.4
±10
13
1.746
1.746
1.746
1.746
1.789
1.789
1.746
1.746
1.746
3.20
3.20
3.20
1.8
1.8
1.8
1.8
1.845
1.845
1.8
1.8
1.8
3.3
3.3
3.3
1.854
1.854
1.854
1.854
1.90
1.90
1.854
1.854
1.854
3.40
3.40
3.40
Max
Unit
Bits
LSB
LSB
LSB
LSB
V
V
μA
μA
μA
μA
pF
V
V
μA
V
V
μA
pF
V
V
V
V
V
V
V
V
V
V
V
V
INL
INL
DNL
DNL
V
IH
V
IL
I
IN
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
HDMI Ethernet and audio channel
(HEAC_x±) inputs
DDR_DQS[x] inputs
Other digital inputs
RESET
Input Capacitance
DIGITAL INPUTS (5 V TOLERANT)
Input High Voltage
Input Low Voltage
Input Leakage Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage
Current
Output Capacitance
POWER REQUIREMENTS
3, 4
Digital Power Supplies
PLL Analog Supply
PLL Digital Supply
Encoder PLL Supply
HDMI PLL Power Supply
5
Transmitter 1 (Tx1)
Transmitter 2 (Tx2)
HDMI Analog Power Supply
Tx1
Tx2
Comparator Power Supply
HDMI Rx Inputs Analog
Supply
Encoder Analog Power
Supply
Digital Interface Supply
C
IN
V
IH
V
IL
I
IN
V
OH
V
OL
I
LEAK
C
OUT
DVDD, DVDD_DDR,
PVDD_DDR
PVDD1
PVDD2
PVDD3
PVDD5
PVDD6
AVDD3
AVDD4
CVDD1
AVDD1
AVDD2
DVDD_IO
Rev. 0 | Page 5 of 52
RF/Wirelessly
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