M7AFS600-FG484I datasheet, PDF

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M7AFS600-FG484I: DescriptionFPGA - Field Programmable Gate Array Fusion; CategoryProgrammable logic devices Programmable logic; File Size18MB，331 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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M7AFS600-FG484I Overview

FPGA - Field Programmable Gate Array Fusion

M7AFS600-FG484I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	1.0 MM PITCH, BGA-484
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B484
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	3
Equivalent number of gates	600000
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	600000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.44 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	23 mm
Base Number Matches	1

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Revision 6

Fusion Family of Mixed Signal FPGAs

Features and Benefits

High-Performance Reprogrammable Flash

Technology

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS

Process

• Nonvolatile, Retains Program when Powered Off

• Instant On Single-Chip Solution

• 350 MHz System Performance

In-System Programming (ISP) and Security

• ISP with 128-Bit AES via JTAG

• FlashLock

Designed to Protect FPGA Contents

Advanced Digital I/O

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS,

M-LVDS

– Built-In I/O Registers

– 700 Mbps DDR Operation

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and

Weak Pull-Up/Down Resistor

• Pin-Compatible Packages across the Fusion

Family

Embedded Flash Memory

• User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

• 1 Kbit of Additional FlashROM

Integrated A/D Converter (ADC) and Analog I/O

•

Up to 12-Bit Resolution and up to 600 Ksps

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High-Voltage Input Tolerance: –10.5 V to +12 V

Current Monitor and Temperature Monitor Blocks

Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA, and 20 mA Drive

Strengths

• ADC Accuracy is Better than 1%

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2,

×4, ×9, and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

Soft ARM Cortex-M1 Fusion Devices (M1)

• ARM

Cortex-™M1–Enabled

On-Chip Clocking Support

•

Internal 100 MHz RC Oscillator (accurate to 1%)

Crystal Oscillator Support (32 KHz to 20 MHz)

Programmable Real-Time Counter (RTC)

6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350

MHz

Pigeon Point ATCA IP Support (P1)

• Targeted to Pigeon Point

Board Management

Reference (BMR) Starter Kits

• Designed in Partnership with Pigeon Point Systems

• ARM Cortex-M1 Enabled

• Targeted to Advanced Mezzanine Card (AdvancedMC™

Designs)

• Designed in Partnership with MicroBlade

• 8051-Based Module Management Controller (MMC)

MicroBlade Advanced Mezzanine Card Support (U1)

Low Power Consumption

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low-Power Modes

Table 1 • Fusion Family

Fusion Devices

ARM Cortex-M1 Devices

Pigeon Point Devices

MicroBlade Devices

System Gates

General

Information

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

Memory

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Analog and I/Os

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

90,000

2,304

Yes

1,024

U1AFS250

250,000

6,144

Yes

1,024

114

AFS090

AFS250

M1AFS250

AFS600

M1AFS600

P1AFS600

U1AFS600

600,000

13,824

Yes

1,024

108

172

AFS1500

M1AFS1500

P1AFS1500

U1AFS1500

1,500,000

38,400

Yes

1,024

270

252

Note:

*Refer to the

Cortex-M1

product brief for more information.

March 2014

Fusion Family of Mixed Signal FPGAs

Table of Contents

Fusion Device Family Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Device Architecture

Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-126

User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-223

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-228

DC and Power Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Package Pin Assignments

QN108

QN180

PQ208

FG256

FG484

FG676

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

Revision 6

Recommended Resources

Analog Circuit--Miscellaneous Talk on Rectification

LA6510 audio IC amplifier circuit diagram

Multiple switch control system circuit diagram

Weak charge signal amplifier circuit

Computer motherboard circuit diagram 440LX_07

Computer motherboard circuit diagram 820 1_64

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