MT8931C
CMOS ST-BUS™ FAMILY
Subscriber Network Interface Circuit
Features
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ETS 300-012, CCITT I.430 and ANSI T1.605
S/T interface
Full-duplex 2B+D, 192 kbit/s transmission
Link activation/deactivation
D-channel access contention resolution
Point-to-point, point-to-multipoint and star
configurations
Master (NT)/Slave (TE) modes of operation
Exceeds loop length requirements
Complete loopback testing capabilities
On chip HDLC D-channel protocoller
8 bit Motorola/Intel microprocessor interface
Microprocessor-controlled operation
Mitel ST-BUS interface
Low power CMOS technology
Single 5 volt power supply
ISSUE 4
November 1997
Ordering Information
MT8931CE
28 Pin Plastic DIP
MT8931CP
44 Pin PLCC
-40°C to +85°C
Description
The MT8931C Subscriber Network Interface Circuit
(SNIC) implements the ETSI ETS 300-012, CCITT
I.430 and ANSI T1.605 Recommendations for the
ISDN S and T reference points. Providing point-to-
point and point-to-multipoint digital transmission, the
SNIC may be used at either end of the subscriber
line (NT or TE).
An HDLC D-channel protocoller is included and
controlled through a Motorola/Intel microprocessor
port.
The MT8931C is fabricated in Mitel’s CMOS process.
Applications
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ISDN NT1
ISDN S or T interface
ISDN Terminal Adaptor (TA)
Digital sets (TE1) - 4 wire ISDN interface
Digital PABXs, Digital Line Cards (NT2)
DSTi
DSTo
ST-BUS
Interface
D-channel Priority
Mechanism
LTx
S-Bus
Link
Interface
VBias
LRx
F0od
C4b
F0b
STAR/Rsto
XTAL1/NT
XTAL2/NC
Microprocessor Interface
VSS
Timing
and
Control
PLL
HDLC
Transceiver
Link
Activation
Controller
VDD
Rsti
HALF
AD0-7
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
Figure 1 - Functional Block Diagram
9-71
MT8931C
NC
NC
F0b
C4b
HALF
NC
VDD
VBias
LTx
NC
LRx
F0od
DSTi
DSTo
NC
NC
NC
XTAL2/NC
XTAL1/NT
NC
R/W/WR
DS/RD
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AS/ALE
CS
IRQ/NDA
VSS
NC
AD0
AD1
AD2
NC
NC
44 PIN PLCC
NC
STAR/Rsto
Rsti
NC
AD7
AD6
NC
AD5
AD4
AD3
NC
HALF
C4b
F0b
F0od
DSTi
DSTo
XTAL2/NC
XTAL1/NT
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VBias
LTx
LRx
STAR/Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
28 PIN PDIP
Figure 2 - Pin Connections
Pin Description
Pin #
DIP PLCC
1
2
Name
HALF
Description
HALF Input/Output:
this is an input in NT mode and an output in TE mode identifying
which half of the S-interface frame is currently being written/read over the ST-BUS
(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,
identifies the information to be transmitted/received in the first half of the S-Bus frame
while HALF=1 identifies the information to be transmitted/received into the second half
of the S-Bus frame). Tying this pin to V
SS
or V
DD
in NT mode will allow the device to free
run. This signal can also be accessed from the ST-BUS C-channel.
4.096 MHz Clock:
a 4.096 MHz ST-BUS Data Clock input in NT mode.
In TE mode an output 4.096 MHz clock phase-locked to the line data signal.
Frame Pulse:
an active low frame pulse input indicating the beginning of active ST-
BUS channel times in NT mode. Frame pulse output in TE mode.
Delayed Frame Pulse Output:
an active low delayed frame pulse output indicating
the end of active ST-BUS channels for this device. Can be used to daisy chain
to other ST-BUS devices to share an ST-BUS stream.
Data ST-BUS Input:
a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2
channels assigned to the first four timeslots. These channels contain data to be
transmitted on the line and chip control information.
Data ST-BUS Output:
a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and
B2 channels assigned to the first four timeslots, respectively. The remaining timeslots
are placed into high impedance. These channels contain data received from the line
and chip status information.
2
3
4
3
4
7
C4b
F0b
F0od
5
8
DSTi
6
9
DSTo
7
13
XTAL2/IC
Crystal 2/Internal Connection:
in TE mode, XTAL1 and XTAL2 are to be connected to
an external 4.096 MHz parallel resonant crystal for the on-chip oscillator.
If XTAL1 is connected directly to a 4.096 MHz clock, this pin must be left unconnected.
In NT mode, this pin must be left unconnected.
XTAL1/NT
Crystal 1/Network Termination Mode Select Input:
for TE mode mode selection, a
4.096 MHz crystal is to be connected between the XTAL1 and XTAL2 pins, or a 4.096
MHz clock can be connected directly to XTAL1. For NT mode selection, this pin must
be tied to VDD. A pull-up resistor is needed when driven by a TTL device.
8
14
9-72
MT8931C
Pin Description (continued)
Pin #
DIP PLCC
9
10
16
17
Name
R/W
/
WR
DS/RD
Description
Read/Write or Write Input:
defines the data bus transfer as a read (R/W=1) or a write
(R/W=0) in Motorola bus mode. Redefined to WR in Intel bus mode.
Data Strobe/Read Input:
active high input indicates to the SNIC that valid data is on
the bus during a write operation or that the SNIC must output data during a read
operation in Motorola bus mode. Redefined to RD in Intel bus mode.
Address Strobe/Address Latch Enable Input:
in Motorola bus mode the falling edge
is used to strobe the address into the SNIC during microprocessor access. Redefined
to ALE in Intel bus mode.
Chip Select Input:
active low, used to select the SNIC for microprocessor access.
Interrupt Request (Open Drain Output):
an output indicating an unmasked HDLC
interrupt. The interrupt remains active until the microprocessor clears it by reading the
HDLC Interrupt Status Register. This interrupt source is enabled with B2=0 of Master
Control Register.
New Data Available (Open Drain Output):
an active low output signal indicating
availability of new data from the S-Bus. This signal is selected with B2=1 of Master
Control Register. This pin must be tied to V
DD
with a 10kΩ resistor.
Ground.
Bidirectional Address/Data Bus:
electrically and logically compatible to either Intel or
Motorola micro-bus specifications. If DS/RD is low on the rising edge of AS/ALE then
the chip operates to Motorola specs. If DS/RD is high on the rising edge of AS/ALE Intel
mode is selected. Taking Rsti low sets Motorola mode.
Reset Input:
Schmitt trigger reset input. If ’0’, sets all control registers to the default
conditions, resets activation state machines to the deactivated state, resets HDLC,
clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode.
11
19
AS/ALE
12
13
20
21
CS
IRQ
NDA
14
22
V
SS
AD0-7
15- 24-26,
22 30-32,
34-35
23
37
Rsti
24
38
STAR/Rsto
Star/Reset (Open Drain Output):
192kbit/s Rx data output fixed relative to the ST-
BUS timebase. A group of NTs, in fixed timing mode, can be wire or’ed together to
create a Star configuration. Active low reset output in TE mode indicating 128
consecutive marks have been received. Can be connected directly to Rsti to allow NT
to reset all TEs on the bus. This pin must be tied to V
DD
with a 10 kΩ resistor.
LRx
Receive Line Signal Input:
this is a high impedance input for the pseudoternary line
signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and
21. A DC bias level on this input equal to V
Bias
must be maintained.
Transmit Line Signal Output:
this is a current source output designed to drive a
nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21.
Bias Voltage:
analog ground for Tx and Rx transformers. This pin must be decoupled
to V
DD
through a 10µF capacitor with good high frequency characteristics.
Power Supply Input.
No Connection.
25
40
26
27
28
42
43
44
1,5-6,10-
12,15,18,
23,27-
29, 33,
36, 39,
41
LTx
V
Bias
V
DD
NC
9-73
MT8931C
Functional Description
The MT8931C Subscriber Network Interface Circuit
(SNIC) is a multifunction transceiver providing a
complete interface to the S/T Reference Point as
specified in ETS 300-012, CCITT Recommendation
I.430 and ANSI T1.605.
Implementing both
point-to-point and point-to-multipoint voice/data
transmission, the SNIC may be used at either end of
the digital subscriber loop. A programmable digital
interface allows the MT8931C to be configured as a
Network Termination (NT) or as a Terminal
Equipment (TE) device.
The SNIC supports 192 kbit/s (2B+D + overhead) full
duplex data transmission on a 4-wire balanced
transmission line. Transmission capability for both B
and D channels, as well as related timing and
synchronization functions, are provided on chip. The
signalling capability and procedures necessary to
enable customer terminals (TEs) to be activated and
deactivated, form part of the MT8931C’s
functionality. The SNIC handles D-channel resource
allocation and prioritization for access contention
resolution and signalling requirements in passive bus
line configurations. Control and status information
allows implementation of mainten-ance functions
and monitoring of the device and the subscriber loop.
An HDLC transceiver is included on the SNIC for link
access protocol handling via the D-channel.
Depacketized data is passed to and from the
transceiver via the microprocessor port. Two 19 byte
deep FIFOs, one for transmit and one for receive, are
provided to buffer the data. The HDLC block can be
set up to transmit or receive to/from either the
S-interface port or the ST-BUS port. Further, the
transmit destination and receive source can be
independently selected, e.g., transmit to S-interface
while receiving from ST-BUS. The transmit and
receive paths can be separately enabled or disabled.
Both, one and two byte address recognition is
supported by the SNIC. A transparent mode allows
data to be passed directly to the D channel without
being packetized.
A block diagram of the MT8931C is shown in Figure
1. The SNIC has three interface ports: a 4-wire
CCITT compatible S/T interface (subscriber loop
interface), a 2048 kbit/s ST-BUS serial port, and a
general purpose parallel microprocessor port. This
8-bit parallel port is compatible with both Motorola or
Intel microprocessor bus signals and timing.
The three major blocks of the MT8931C, consisting
of the system serial interface (ST-BUS), HDLC
transceiver, and the digital subscriber loop interface
(S-interface) are interconnected by high speed data
busses.
Data sent to and received from the
S-interface port (B1, B2 and D channels) can be
accessed from either the parallel microprocessor
port or the serial ST-BUS port. This is also true for
SNIC control and status information (C-channel).
Depacketized D-channel information to and from the
HDLC section can only be accessed through the
parallel microprocessor port.
S-Bus Interface
The S-Bus is a four wire, full duplex, time division
multiplexed transmission facility which exchanges
information at 192 kbit/s rate including two 64 kbit/s
PCM voice or data channels, a 16 kbit/s signalling
channel and 48 kbit/s for synchronization and
overhead. The relative position of these channels
with respect to the ST-BUS is shown in Figures 4
and 5.
The SNIC makes use of the first four channels on the
ST-BUS to transmit and receive control/status and
data to and from the S-interface port. These are the
B, D and C-channels (see Figure 4).
NT MODE
HALF
C4bi
F0bi
F0od
DSTi
DSTo
Cmode
NT
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VBias
LTx
LRx
STAR
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
HALF
C4bo
F0bo
F0od
DSTi
DSTo
XTAL2
XTAL1
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TE MODE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VBias
LTx
LRx
Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Figure 3 - SNIC Pin Connections
9-74
MT8931C
The B1 and B2 channels each have a bandwidth of
64 kbit/s and are used to carry PCM voice or data
across the network.
B2
B2
B2
B2
B2
B2
B2
B2
The D-channel is primarily intended to carry
signalling information for circuit switching through the
ISDN network. The SNIC provides the capability of
having a 16 kbit/s or full 64 kbit/s D-channel by
allocating the B1-channel timeslot to the D-channel.
Access to the depacketized D-channel is only
granted through the parallel microprocessor port.
B2
B2
B2
B2
Channel 3 (B2)
B2
B2
B2
B2
The C-channel provides a means for the system to
control and monitor the functionality of the SNIC.
This control/status channel is accessed by the
system through the ST-BUS or microprocessor
port.
The C-channel provides access to two
registers which provide complete control over the
state activation machine, the D-channel priority
mechanism as well as the various maintenance
functions. A detailed description of these registers is
discussed in the microprocessor port interface.
B1
B1
B1
B1
B1
B1
B1
B1
Channel 2 (B1)
B1
B1
B1
B1
Output in high impedance state
B1
B1
Don’t care
B1
B1
C0
C0
Line Code
The line code used on the S-interface is a Pseudo
ternary code with 100% pulse width as seen in
Figure 5 below. Binary zeros are represented as
marks on the line and successive marks will
alternate in polarity.
C1
C2
C2
C1
C5
C6
C6
C5
Channel 1 (C)
C3
C4
C4
C3
C7
D7
D7
C7
BINARY
VALUE
0
1
0
0
0
1
0
0
1
1
Only valid with 64 kbit/s D-channel
D6
D6
LINE
SIGNAL
Violation
D5
D5
Channel 0 (D)
D4
D3
D3
D4
Figure 5 - Alternate Zero Inversion Line Code
A mark which does not adhere to the alternating
polarity is known as a bipolar violation.
D2
D1
D0
DSTo
D0
D1
D2
Figure 4 - ST-BUS Channel Assignment
9-75
F0od
DSTi
F0b
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