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NDS8410S

Description
Single N-Channel Enhancement Mode Field Effect Transistor
CategoryDiscrete semiconductor    The transistor   
File Size237KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

NDS8410S Overview

Single N-Channel Enhancement Mode Field Effect Transistor

NDS8410S Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (Abs) (ID)8.6 A
Maximum drain current (ID)8.6 A
Maximum drain-source on-resistance0.02 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)2.5 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
February 1997
NDS8410S
Single N-Channel Enhancement Mode Field Effect Transistor
General Description
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
8.6 A, 30 V. R
DS(ON)
= 0.02
@ V
GS
= 10 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
NDS8410S
30
±20
8.6
30
2.5
1.2
1
-55 to 150
Units
V
V
A
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS8410S Rev.C
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