DATA SHEET
512M bits DDR SDRAM
EDD5104ADTA (128M words
×
4 bits)
EDD5108ADTA (64M words
×
8 bits)
EDD5116ADTA (32M words
×
16 bits)
Description
The EDD5104AD, the EDD5108AD and the
EDD5116AD are 512M bits Double Data Rate (DDR)
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
VDD
VDD
NC
DQ0
DQ0
VDDQ VDDQ VDDQ
NC
NC
DQ1
DQ0
DQ1
DQ2
VSSQ VSSQ VSSQ
NC
NC
DQ3
NC
DQ2
DQ4
VDDQ VDDQ VDDQ
NC
NC
DQ5
DQ1
DQ3
DQ6
VSSQ VSSQ VSSQ
NC
NC
DQ7
NC
NC
NC
VDDQ VDDQ VDDQ
NC
NC LDQS
NC
NC
NC
VDD
VDD
VDD
NC
NC
NC
NC
NC
LDM
/WE
/WE
/WE
/CAS
/CAS
/CAS
/RAS
/RAS
/RAS
/CS
/CS
/CS
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10(AP) A10(AP) A10(AP)
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
DQ14 NC
NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
DQ12 NC
NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
DQ10 NC
NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
DQ8 NC
NC
NC
NC
NC
VSSQ VSSQ VSSQ
UDQS DQS DQS
NC
NC
NC
VREF VREF VREF
VSS VSS VSS
UDM DM
DM
/CK /CK /CK
CK
CK
CK
CKE CKE CKE
NC
NC
NC
A12 A12 A12
A11 A11 A11
A9
A9
A9
A8
A8
A8
A7
A7
A7
A6
A6
A6
A5
A5
A5
A4
A4
A4
VSS VSS VSS
Features
•
Power supply: VDD, VDDQ = 2.5V
±
0.2V
•
Data Rate: 333Mbps/266Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
SSTL_2 compatible I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Programmable output driver strength: normal/weak
•
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0384E30 (Ver. 3.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
X 16
X8
X4
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Elpida
Memory, Inc. 2003-2004
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Ordering Information
Part number
EDD5104ADTA-6B
EDD5104ADTA-7A
EDD5104ADTA-7B
EDD5108ADTA-6B
EDD5108ADTA-7A
EDD5108ADTA-7B
EDD5116ADTA-6B
EDD5116ADTA-7A
EDD5116ADTA-7B
EDD5104ADTA-6BL
EDD5104ADTA-7AL
EDD5104ADTA-7BL
EDD5108ADTA-6BL
EDD5108ADTA-7AL
EDD5108ADTA-7BL
EDD5116ADTA-6BL
EDD5116ADTA-7AL
EDD5116ADTA-7BL
Mask
version
D
Organization
(words
×
bits)
128M
×
4
Internal
banks
4
Data
rate
Mbps (max.)
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
64M
×
8
32M
×
16
D
128M
×
4
4
64M
×
8
32M
×
16
Part Number
E D D 51 04 A D TA - 6B L
Elpida Memory
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Bit Organization
04: x4
08: x8
16: x16
Voltage, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Power Consumption
Blank: Normal
L: Low Power
Data Sheet E0384E30 (Ver. 3.0)
2
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions ..........................................................................................................47
Data Sheet E0384E30 (Ver. 3.0)
3
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
°
Parameter
Supply voltage
Symbol
VDD,
VDDQ
VSS,
VSSQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VIX (DC)
VID (DC)
min
2.3
0
0.49
×
VDDQ
VREF – 0.04
VREF + 0.15
–0.3
–0.3
0.5
×
VDDQ
−
0.2V
0.36
typ
2.5
0
0.50
×
VDDQ
VREF
—
—
—
0.5
×
VDDQ
—
max
2.7
0
0.51
×
VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
Unit
V
V
V
V
V
V
V
2
3
4
Notes
1
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
0.5
×
VDDQ + 0.2V V
VDDQ + 0.6
V
5, 6
Notes: 1.
2.
3.
4.
5.
6.
VDDQ must be lower than or equal to VDD.
VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (DC) specifies the allowable DC execution of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0384E30 (Ver. 3.0)
4
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
max.
Parameter
Operating current (ACT-
PRE)
Operating current
(ACT-READ-PRE)
Symbol
IDD0
IDD1
Grade
-6B
-7A, -7B
-6B
-7A, -7B
×
4
150
135
190
170
3
-6B
-7A, -7B
30
25
20
20
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
65
55
230
200
230
200
320
300
4
-xxL
-6B
-7A, -7B
3
490
410
×
8
150
135
200
175
3
30
25
20
20
65
55
250
210
250
210
320
300
4
3
510
430
×
16
150
135
210
180
3
30
25
20
20
65
55
270
230
270
230
320
300
4
3
530
450
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
BL = 4
1, 5, 6, 7
Test condition
CKE
≥
VIH,
tRC = tRC (min.)
CKE
≥
VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH,
DQ, DQS, DM = VREF
CKE
≥
VIH, /CS
≥
VIH,
DQ, DQS, DM = VREF
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH
tRAS = tRAS (max.)
CKE
≥
VIH, BL = 2,
CL = 2.5
CKE
≥
VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input
≤
VIL or
≥
VIH
Input
≥
VDD – 0.2 V
Input
≤
0.2 V
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Idle power down standby
IDD2P
current
Floating idle standby
IDD2F
current
Quiet idle standby current IDD2Q
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto Refresh current
Self refresh current
Self refresh current
((L-version))
Operating current
(4 banks interleaving)
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD6
IDD7A
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at
≥
VIH or
≤
VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
°
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
ILI
ILO
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
—
—
Unit
µA
µA
mA
mA
Test condition
VDD
≥
VIN
≥
VSS
VDDQ
≥
VOUT
≥
VSS
VOUT = 1.95V
VOUT = 0.35V
Notes
Data Sheet E0384E30 (Ver. 3.0)
5
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