Advance Information
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
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by DSP56166/D
DSP56166
Ceramic Quad Flat Pack (CQFP)
Available in a 112 pin, small footprint,
surface mount package.
16-bit General Purpose
Digital Signal Processor
The DSP56166 is the second member of Motorola’s DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal
Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in
Σ∆
codec and
phase locked loop (PLL). This MPU-style DSP also contains, memories, digital peripherals, and provides a cost effective, high per-
formance solution to many DSP applications. On-Chip Emulation (OnCE
™
) circuitry provides convenient and inexpensive debug fa-
cilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly
simplified by using the OnCE. The DSP56166 RAM based is an off the shelf part since there are no user programmable ROM’s on-
chip. The DSP56166 ROM based contains a 12K ROM (8Kx 16 program ROM and 4Kx16 data ROM).
The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an
instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56166. The MPU-style programming
model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and development tools
of the DSP56100 family, DSP56000 family, and DSP96002 are so similar that learning to design and program one greatly reduces
the time needed to learn the others.
DSP56166ROM Feature List
DSP56100 Family Features
• Up to 30 Million Instructions per Second (MIPS) at 60
MHz.– 33.3 ns Instruction cycle
• Single-cycle 16 x 16-bit parallel Multiply-Accumulate
• 2 x 40-bit accumulators with extension byte
• Fractional and integer arithmetic with support for
multiprecision arithmetic
• Highly parallel instruction set with unique DSP
addressing modes
• Nested hardware DO loops including infinite loops and
DO zero loop
• Two instruction LMS adaptive filter loop
• Fast auto-return interrupts
• Three external interrupt request pins
• Three 16-bit internal data and three 16-bit internal
address buses
• Individual programmable wait states on the external bus
for program, data, and peripheral memory spaces
• Off-chip memory-mapped peripheral space with
programmable access time and separate peripheral
enable pin
• On-chip memory-mapped peripheral registers
• Low Power Wait and Stop modes
• On-Chip Emulation (OnCE
)
for unobtrusive, processor
speed independent debugging
• Operating frequency down to DC
• 5V single power supply
• Low power (HCMOS)
DSP56166ROM On-chip Resources
•
•
•
•
•
•
•
4K x 16 on-chip data RAM
4K x 16 on-chip data ROM
256 x 16 on-chip program RAM
8K x 16 on-chip program ROM
One external 16-bit address bus
One external 16-bit data bus
On-chip
Σ∆
voice band codec (A/D-D/A)
– Internal voltage reference (2/5 of positive power
supply)
•
•
•
•
•
•
– No off-chip components required
25 general purpose I/O pins
On-chip, programmable PLL
Byte-wide Host Interface with DMA support
Two independent reduced synchronous serial
interfaces
One 16-bit timer
112 pin quad flat pack packaging
Operational Differences Of The ROM Based Part From The RAM Based Part
• XROM can only be accessed during a single read or the
first read of a dual parallel read instruction (see note on
page 2)
• Reset mode 1 vectors to P:$0100
• PROM area P:$2080 — P:$20FF is reserved and
should not be programmed or accessed by the user
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA
©
MOTOROLA INC., 1993
6/15/93
INTRODUCTION
This data sheet is intended to be used with the DSP56100 Fam-
ily Manual and the DSP56166 User’s Manual. The DSP56100
Family Manual provides a description of the components of the
DSP5616 core processor that are common to all DSP56100 fam-
ily processors and includes a detailed description of the basic
DSP56100 family instruction set. The DSP56166 User’s Manual
provides a description of the memory and peripherals that are
specific to the DSP56166. The DSP56166 Data Sheet provides
electrical specifications and timings that are specific to the
DSP56166.
The DSP56166 pinout is shown in Figure 3. The input and output
signals on the chip are organized into the 13 functional groups
shown in Table 1.
A15 address lines. PS/DS is high for program memory
access and is low for data memory access. If the external
bus is not used during an instruction cycle (t0,t1,t2,t3),
PS/DS goes high in t0. PS/DS is in the high impedance
state during hardware reset, stop mode and when the DSP
is not the bus master.
PEREN
(Peripheral Enable) — three state active low output.
This output is asserted only when external peripheral space
of the data memory is referenced (any address between
X:$FF00 and X:$FF7F). PEREN timing is the same as the
A0-A15 address lines; it is asserted and deasserted during
t0. PEREN is high for any program memory access and for
data memory access not in the space X:$FF00 - X:$FF7F.
PEREN is in the high impedance state during hardware
reset, stop mode and when the DSP is not the bus master.
R/W
(Read/Write)- three state, active low output. Timing is
the same as for the address lines, providing an “early write”
signal. R/W (which changes in t0) is high for a read access
and is low for a write access. If the external bus is not used
during an instruction cycle (t0,t1,t2,t3), R/W goes high in t0.
R/W is three-stated during hardware reset, stop mode and
when the DSP is not the bus master.
Table 1
Functional Group Pin Allocations
Functional Group
Address and Data Buses
Bus Control
Interrupt and Mode Control
Clock and PLL
Host Interface or PIO
Timer Interface or PIO
RSSI Interfaces or PIO
On-chip CODEC
On-chip emulation (OnCE)
Power (Vdd)
Ground (Vss)
APower (Vdda)
AGround (Vssa)
Total
Number of Pins
32
10
4
3
15
2
8
7
4
9
16
1
1
112
WR
(Write Enable) — three state, active low output. This
output is asserted during external memory write cycles.
When WR is asserted in t1, the data bus pins D0-D15
become outputs and the DSP puts data on the bus during
the leading edge of t2. When WR is deasserted in t3, the
external data has been latched inside the external device.
When WR is asserted, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to the WE pin of a static
RAM. WR is three-stated during hardware reset, stop mode
and when the DSP is not the bus master.
(Read Enable) — three state, active low output. This
output is asserted during external memory read cycles.
When RD is asserted in late t0/early t1, the data bus pins
D0-D15 become inputs and an external device is enabled
onto the data bus. When RD is deasserted in t3, the
external data has been latched inside the DSP. When RD
is asserted, it qualifies the A0-A15 and PS/DS pins. RD can
be connected directly to the OE pin of a static RAM or ROM.
RD is three-stated during hardware reset, stop mode and
when the DSP is not the bus master.
(Bus Strobe) — active low output. Asserted at the start
of a bus cycle (during t0) and deasserted at the end of the
bus cycle (during t2). This pin provides an “early bus start”
signal which can be used as address latch and as an “early
bus end” signal which can be used by an external bus
controller. BS is three-stated during hardware reset, stop
mode and when the DSP is not the bus master.
(Transfer Acknowledge) — active low input. If there is
no external bus activity, the TA input is ignored by the DSP.
When there is external bus cycle activity, TA can be used
to insert wait states in the external bus cycle. TA is sampled
on the leading edge of the clock. Any number of wait states
from 1 to infinity may be inserted by using TA. If TA is
sampled high on the leading edge of the clock beginning
the bus cycle, the bus cycle will end 2T after the TA has
been sampled low on a leading edge of the clock; if the Bus
Control Register (BCR) value does not program more wait
RD
ADDRESS AND DATA BUS (32 PINS
A0-A15
(Address Bus) — three state, active high outputs. A0-
A15 change in t0 and specify the address for external
program and data memory accesses. If there is no external
bus activity, A0-A15 remain at their previous values. A0-
A15 are three-stated during hardware reset, stop mode and
when the DSP is not the bus master.
D0-D15
(Data Bus) — three state, active high, bidirectional
input/outputs. Read data is sampled on the trailing edge of
t2, while write data output is enabled by the leading edge of
t2 and three-stated at the leading edge of t0. If there is no
external bus activity, D0-D15 are three-stated. D0-D15 are
also three-stated during hardware reset.
BS
TA
BUS CONTROL (10 PINS)
PS/DS
(Program /Data Memory Select) — three state active
low output. This output is asserted only when external data
memory is referenced. PS/DS timing is the same for the A0-
DSP56166
PRELIMINARY
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