DATASHEET
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Description
The IDT5V41067A is a 2:4 differential clock mux for PCI
Express applications. It has very low additive jitter making it
suitable for use in PCIe Gen2 and Gen3 systems. The
IDT5V41067A selects between 1 of 2 differential HCSL
inputs to fanout to 4 differential HCSL output pairs. The
outputs can also be terminated to LVDS.
IDT5V41067A
Features/Benefits
•
Low additive jitter; suitable for use in PCIe Gen2 and
•
•
•
•
Gen3 systems
20-pin TSSOP package; small board footprint
Outputs can be terminated to LVDS; can drive a wider
variety of devices
OE control pin; greater system power management
Industrial temperature range available; supports
demanding embedded applications
Recommended Applications
•
Clock muxing in PCIe Gen2 and Gen3 applications
Output Features
•
4 – 0.7V current mode differential HCSL output pairs
Key Specifications
•
Additive cycle-to-cycle jitter <5 ps
•
Additive phase jitter (PCIe Gen2/3) <0.2ps
•
Operating frequency up to 200MHz
Block Diagram
VDD
2
OE
CLKA
CLKA
IN1
IN1
IN2
IN2
MUX
2 to 1
CLKB
CLKB
CLKC
CLKC
CLKD
CLKD
2
SEL
GND
PD
Rr (IREF)
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
1
IDT5V41067A
REV F 112211
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Pin Assignment
^SEL
VDDIN
DIF_IN1
DIF_IN1#
^PD#
DIF_IN2
DIF_IN2#
^OE
GND
IR EF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
Select Table
SEL
0
1
Outputs
DIF_IN2
DIF_IN1
Note:
Pins preceeded by '*^ have internal
120K ohm pull up resistors
20-pin (173mil) TSSOP
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
^SEL
VDDIN
DIF_IN1
DIF_IN1#
^PD#
DIF_IN2
DIF_IN2#
^OE
GND
IREF
DIF_3#
DIF_3
DIF_2#
DIF_2
VDD
GND
DIF_1#
DIF_1
DIF_0#
DIF_0
PIN TYPE
IN
PWR
IN
IN
IN
IN
IN
IN
PWR
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Selects between one of two inputs . This pin has internal pull up resis tor.
Power pin for the Inputs, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Asynchronous active low input pin used to power down the device. The internal
c locks are dis abled and the VCO and the crystal os c. (if any) are stopped.
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Activ e high input for enabling outputs. This pin has an internal pull up resistor.
0 = disable outputs, 1= enable outputs
Ground pin.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the s tandard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
5V41067
2
IDT5V41067A
REV F 112211
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5V41067A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41067A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41067A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the
Layout Guidelines
section.
The IDT5V41067A can also be terminated to LVDS
compatible voltage levels. See the
Layout Guidelines
section.
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
3
IDT5V41067A
REV F 112211
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Output Structures
IREF
=2.3 mA
6*IREF
R
R
475
See Layout Guidelines
Sections - Pages 5, 6
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41067A.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
4
IDT5V41067A
REV F 112211
IDT5V41067A
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
Layout Guidelines
PCIe (SRC) R eference Clock
Common Recommendations for Differential Routing
D imension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L1
Rs
L2
L4
L4'
L2'
Rs
Rt
Rt
PCI Express
Down Device
REF_CLK Input
L1'
HCSL Output Buffer
L3'
L3
Figure 2: PCI Express Connector Routing
L1
Rs
L2
L4
L4'
L2'
Rs
Rt
Rt
PCI Express
Add-in Board
REF_CLK Input
L1'
HCSL Output Buffer
L3'
L3
IDT®
2:4 PCIE GEN1/2/3 CLOCK MULTIPLEXER
5
IDT5V41067A
REV F 112211
ST - Low Power RF
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