5962-8946803XX datasheet, PDF - EEWORLD Datasheet

5962-8946803XX: DescriptionUV PLD, 51ns, CMOS, CPGA68, CERAMIC, PGA-68; CategoryProgrammable logic devices Programmable logic; File Size618KB，17 Pages; ManufacturerCypress Semiconductor

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5962-8946803XX Overview

UV PLD, 51ns, CMOS, CPGA68, CERAMIC, PGA-68

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	PGA,
Contacts	68
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
JESD-30 code	S-CPGA-P68
Dedicated input times	7
Number of I/O lines	52
Number of terminals	68
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	7 DEDICATED INPUTS, 52 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Programmable logic type	UV PLD
propagation delay	51 ns
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal location	PERPENDICULAR
Base Number Matches	1

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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