INTEGRATED CIRCUITS
OM5234/OM5284
CMOS single-chip 8-bit microcontrollers
Preliminary specification
1996 Nov 01
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
OM5234/OM5284
DESCRIPTION
The OM5234 and OM5284 single-chip 8-bit microcontrollers are
manufactured in an advanced CMOS process and are derivatives of
the 80C51 microcontroller family. The OM5234 and OM5284 are
pre-programmed devices for specific applications. Unless
specifically stated otherwise, all references to OM5234 apply equally
to OM5284.
The OM5234 contains a non-volatile 16k
×
8 read-only program
memory, a volatile 256
×
8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a multi-source, two-priority-level, nested interrupt structure,
UART and on-chip oscillator and timing circuits.
FEATURES
•
80C51 central processing unit
•
6k
×
8 ROM
•
256
×
8 RAM
•
Two standard 16-bit timer/counters
•
Four 8-bit I/O ports
•
Full-duplex UART facilities
•
Power control modes
–
Idle mode
–
Power-down mode
•
ROM code protection
ORDERING INFORMATION
OM5234 / F T P / YYY
Device
OM5234
Frequency Range
F = 3.5 to 16MHz
I = 3.5 to 24MHz
Temperature Range
B = 0 to 70°C
PART NUMBER
OM5234/FBB/YYY
OM5234/FBP/YYY
OM5234/FBA/YYY
OM5284EBYY
OM5284EAYY
OM5284EPYY
ROM code for application
5XX, etc.
Package designator
A = Plastic Leaded Chip Carrier
B = Plastic Quad Flat Package
P = Plastic Dual In-Line Package
Device
OM5284
Frequency Range
E = 3.5 to 16MHz
I = 3.5 to 24MHz
OM5284 X Y ZZ
ROM code for application
01, 02, 03
Package designator
A = Plastic Leaded Chip Carier
B = Plastic Quad Flat Package
P = Plastic Dual In-Line Package
FREQUENCY
(MHz)
16
16
16
16
16
16
DRAWING
NUMBER
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT187-2
SOT129-1
TEMPERATURE RANGE
°C
AND PACKAGE
0 to 70°C, Plastic Quad Flat Package
0 to 70°C, Plastic Dual In-Line Package
0 to 70°C, Plastic Leaded Chip Carrier
0 to 70°C, Plastic Quad Flat Package
0 to 70°C, Plastic Leaded Chip Carrier
0 to 70°C, Plastic Dual In-Line Package
LOGIC SYMBOL
V
CC
V
SS
RST
PORT 0
XTAL1
XTAL2
EA
PSEN
ALE
ADDRESS AND
DATA BUS
ALTERNATE
FUNCTIONS
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
SU00800
1996 Nov 01
2
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
OM5234/OM5284
PIN CONFIGURATIONS
DUAL IN-LINE PACKAGE
PIN FUNCTIONS
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
1
2
3
4
5
6
7
8
9
DUAL
IN-LINE
PACKAGE
40 V
DD
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
17
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
NC*
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
18
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
28
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
29
PLCC
7
39
PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
6
1
40
P3.0/RxD 10
P3.1/TxD 11
P3.2/INT0 12
P3.3/INT1 13
P3.4/T0 14
P3.5/T1 15
P3.6/WR 16
P3.7/RD 17
XTAL2 18
XTAL1 19
V
SS
20
* DO NOT CONNECT
SU00798
SU00802
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
1
33
PQFP
11
23
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5
P1.6
P1.7
RST
P3.0/RxD
V
SS4
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
V
SS1
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
V
SS2
EA/V
PP
P0.7/AD7
22
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
V
SS3
P1.0
P1.1
P1.2
P.13
P1.4
SU00799
1996 Nov 01
3
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
OM5234/OM5284
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC PLCC
V
SS
V
DD
P0.0–0.7
22
44
43–36
QFP
6, 16,
28, 39
38
37–30
DIP
20
40
39–32
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference. With the QFP package, all V
SS
pins (V
SS1
to V
SS4
) must be
connected.
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7,
which are open drain for OM5234 (only). Port 1 pins that have 1s written to them are
pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I
IL
). Alternate functions include:
Bidirectional I/O with internal pull-ups (OM5284), and open drain for (OM5234).
Bidirectional I/O with internal pull-ups (OM5284), and open drain for (OM5234).
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of
the 80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an
external capacitor to V
CC
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to
external data memory.
Program Store Enable:
Read strobe to external program memory via Port 0 and Port 2.
It is activated twice each machine cycle during fetches from the external program
memory. When executing out of external program memory, two activations of PSEN are
skipped during each access to external data memory. PSEN is not activated (remains
HIGH) during fetches from external program memory. PSEN can sink/source 8 LSTTL
inputs and can drive CMOS inputs without external pull-ups.
External Access:
If during a RESET, EA is held at TTL, level HIGH, the CPU executes
out of the internal program memory ROM provided the Program Counter is less than
16384. If during a RESET, EA is held at TTL LOW level, the CPU executes out of external
program memory. EA is not allowed to float.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
P1.0–P1.7
2–9
40–44,
1–3
1–8
I/O
P1.6
P1.7
P2.0–P2.7
8
9
24–31
2
3
18–25
7
8
21–28
I/O
I/O
I/O
P3.0–P3.7
11,
13–19
5,
7–13
10–17
I/O
11
13
14
15
16
17
18
19
RST
10
5
7
8
9
10
11
12
13
4
10
11
12
13
14
15
16
17
9
I
O
I
I
I
I
O
O
I
ALE
33
27
30
I/O
PSEN
32
26
29
O
EA
35
29
31
I
XTAL1
21
15
19
I
XTAL2
20
14
18
O
Crystal 2:
Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
DD
+ 0.5V or V
SS
– 0.5V, respectively.
1996 Nov 01
4
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
OM5234/OM5284
DC ELECTRICAL CHARACTERISTICS
V
SS
= 0V, V
DD
= 5V
±
10%, T
amb
= 0°C to +70°C
TEST
SYMBOL
V
IL
V
IL1
V
IL2
V
IH
V
IH1
V
OL
V
OL1
V
OL2
V
OH
I
IL
I
TL
I
L1
I
DD
PARAMETER
Input low voltage, except EA, P1.6, P1.7
Input low voltage to EA
Input low voltage to P1.6, P1.7
Input high voltage, except XTAL1, RST, P1.6, P1.7
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3, except P1.6, P1.7
Output low voltage, port 0, ALE, PSEN
Output low voltage, P1.6, P1.7
Output high voltage, ports 1, 2, 3, ALE, PSEN
8
Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7
Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6, P1.7
Input leakage current, port 0, EA, P1.6, P1.7
Power supply current:
Active mode @ 16MHz
1, 9
Idle mode @ 16MHz
2, 9
Power down mode
3, 4
Internal reset pull-down resistor
Pin capacitance
I
OL
= 1.6mA
6, 7
I
OL
= 3.2mA
6, 7
I
OL
= 3.0mA
I
OH
= –25µA
V
IN
= 0.45V
See note 5
0.45V < V
I
< 4.7V
V
DD
=5.5V
0.75V
DD
–50
–650
±10
32.0
6
50
40
225
15
CONDITIONS
MIN.
–0.5
–0.5
–0.5
0.2V
DD
+0.9
0.7V
DD
LIMITS
MAX.
0.2V
DD
–0.1
0.2V
DD
–0.3
0.3V
DD
V
DD
+0.5
V
DD
+0.5
0.45
0.45
0.4
UNIT
V
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
µA
kΩ
pF
R
RST
C
IO
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns;
V
IL
= V
SS
+ 0.5V; V
IH
= V
DD
–0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V
DD
.
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns; V
IL
= V
SS
+ 0.5V;
V
IH
= V
DD
–0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
DD
; EA = RST = V
SS
.
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V
DD
;
EA = RST = V
SS
.
4. 2V
≤
V
PD
≤
V
DD
max.
5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2V.
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
7. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows: Maximum I
OL
= 10mA per port pin; Maximum
I
OL
= 26mA total for Port 0; Maximum I
OL
= 15mA total for Ports 1, 2, and 3; Maximum I
OL
= 71mA total for all output pins. If I
OL
exceeds the
test conditions, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the
address bits are stabilizing.
9. I
DDMAX
for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I
DDMAX
is given in mA.
1996 Nov 01
5
EE_FPGA Learning Park
京公网安备 11010802033920号
EEWORLD
