PPC440SP-ANC533C datasheet, PDF

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PPC440SP-ANC533C: Descriptionpowerpc 440sp embedded processor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size629KB，85 Pages; ManufacturerApplied Micro Circuits (MACOM); Environmental Compliance

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PPC440SP-ANC533C Overview

powerpc 440sp embedded processor

PPC440SP-ANC533C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	BGA, BGA783,28X28,40
Contacts	783
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	666.66 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
length	29 mm
low power mode	YES
Number of terminals	783
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA783,28X28,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,1.8,2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	3.27 mm
speed	533 MHz
Maximum slew rate	3000 mA
Maximum supply voltage	1.6 V
Minimum supply voltage	1.4 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Part Number 440SP

Revision 1.23 - Sept 26, 2006

Data Sheet

PowerPC 440SP Embedded Processor

Features

• PowerPC

‚

440 processor core operating at up to

667MHz with 32-KB I- and D-caches (with parity

checking)

• On-chip 256-KB SRAM configurable as L2 Cache

or Ethernet Packet/Code store memory

• Selectable Processor:Bus clock ratios (Refer to

the Clocking chapter in the

PPC440SP Embedded

Processor User’s Manual

for details)

• Supports up to 4 GB (2 Chip Selects) of 64-bit/32-

bit SDRAM with ECC

– DDR1 266-333-400

– DDR2 400-533-667

• Three DDR PCI-X interfaces (32-bit or 64-bit) up

to 133 MHz (DDR 266) with support for

conventional PCI

• XOR Accelerator with DMA controller

• Processor can boot from PCI memory

• Optional: High throughput RAID 6 hardware

acceleration, performs XOR and Galois Field P &

Q parity computations, supports up to 255 drives

• I2O Messaging Unit with two DMA controllers

• External Peripheral Bus (24-bit Address, 8-bit

Data) for up to three devices

• One Ethernet 10/100/1000 Mbps half- or full-

duplex interface. Operational modes supported

are MII and GMII.

• Programmable Interrupt Controller supports

interrupts from a variety of sources.

• Programmable General Purpose Timers (GPT)

• Three serial ports (16750 compatible UART)

• Two IIC interfaces

• General Purpose I/O (GPIO) interface available

• JTAG interface for board level testing

Description

Designed specifically to address high-end embedded

applications for storage, the PowerPC 440SP

Embedded Processor (PPC440SP) provides a high-

performance, low power solution that interfaces to a

wide range of peripherals by incorporating on-chip

power management features and lower power

dissipation.

This chip contains a high-performance RISC

processor core, a DDR2 SDRAM controller,

configurable 256KB SRAM to be used as L2 cache or

software-controlled on-chip memory, three DDR PCI-X

bus interfaces, an Ethernet interface, an I2O/DMA

controller, control for external ROM and peripherals,

optional RAID 6 acceleration, an XOR DMA unit, serial

ports, IIC interfaces, and general purpose I/O.

Technology: CMOS Cu-11, 0.13mm

Package: 29mm, 783-ball, 1mm pitch, Flip Chip-

Plastic Ball Grid Array (FC-PBGA)

Power (estimated): Less than 6W @533MHz

Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

PowerPC 440SP Embedded Processor

Contents

Data Sheet

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

Figures

PowerPC 440SP Embedded Processor

Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. 29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 5. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 9. DDR SDRAM Read Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 11. DDR SDRAM Read Cycle Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Tables

Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 15. I/O Specifications—533MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 18. DDR SDRAM Clock to Write DQS Timing—TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 20. DDR SDRAM I/O Read Timing—T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

AMCC Proprietary

PPC440SP-ANC533C Related Products

	PPC440SP-ANC533C	PPC440SP-ANC667C	PPC440SP	PPC440SP-RFC667C	PPC440SP-AFC533C	PPC440SP-RNC667C	PPC440SP-AFC667C	PPC440SP-RNC533C	PPC440SP-RFC533C
Description	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor	powerpc 440sp embedded processor
Is it Rohs certified?	conform to	conform to	-	incompatible	incompatible	conform to	incompatible	conform to	incompatible
Maker	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	-	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)
Parts packaging code	BGA	BGA	-	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40	-	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40	BGA, BGA783,28X28,40
Contacts	783	783	-	783	783	783	783	783	783
Reach Compliance Code	compliant	compliant	-	compliant	compliant	compliant	unknown	compliant	compliant
ECCN code	3A001.A.3	3A001.A.3	-	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	32	32	-	32	32	32	32	32	32
bit size	32	32	-	32	32	32	32	32	32
boundary scan	YES	YES	-	YES	YES	YES	YES	YES	YES
maximum clock frequency	666.66 MHz	666.66 MHz	-	666.66 MHz	666.66 MHz	666.66 MHz	666.66 MHz	666.66 MHz	666.66 MHz
External data bus width	64	64	-	64	64	64	64	64	64
Format	FIXED POINT	FIXED POINT	-	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	-	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-B783	S-PBGA-B783	-	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783	S-PBGA-B783
length	29 mm	29 mm	-	29 mm	29 mm	29 mm	29 mm	29 mm	29 mm
low power mode	YES	YES	-	YES	YES	YES	YES	YES	YES
Number of terminals	783	783	-	783	783	783	783	783	783
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	-	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA783,28X28,40	BGA783,28X28,40	-	BGA783,28X28,40	BGA783,28X28,40	BGA783,28X28,40	BGA783,28X28,40	BGA783,28X28,40	BGA783,28X28,40
Package shape	SQUARE	SQUARE	-	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	-	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V	1.5,1.8,2.5,3.3 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.27 mm	3.27 mm	-	3.27 mm	3.27 mm	3.27 mm	3.27 mm	3.27 mm	3.27 mm
speed	533 MHz	667 MHz	-	667 MHz	533 MHz	667 MHz	667 MHz	533 MHz	533 MHz
Maximum slew rate	3000 mA	3000 mA	-	3000 mA	3000 mA	3000 mA	3000 mA	3000 mA	3000 mA
Maximum supply voltage	1.6 V	1.575 V	-	1.575 V	1.6 V	1.575 V	1.575 V	1.6 V	1.6 V
Minimum supply voltage	1.4 V	1.425 V	-	1.425 V	1.4 V	1.425 V	1.425 V	1.4 V	1.4 V
Nominal supply voltage	1.5 V	1.5 V	-	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	-	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	-	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	-	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	29 mm	29 mm	-	29 mm	29 mm	29 mm	29 mm	29 mm	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1	-	1	1	1	1	1	1

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