SL74HC374
Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The SL74HC374 is identical in pinout to the LS/ALS374. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of the Clock. The Output Enable input does not affect
the states of the flip-flops, but when Output Enable is high, the
outputs are forced to the high-impedance state; thus, data may be
stored even when the outputs are not enabled.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC374N Plastic
SL74HC374D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=V
CC
PIN 10 = GND
Inputs
Output
Enable
L
L
L
H
L,H,
X
Clock
D
H
L
X
X
Output
Q
H
L
no
change
Z
X = don’t care
Z = high impedance
SLS
System Logic
Semiconductor
SL74HC374
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±35
±75
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC374
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5.0
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±10
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
6.0 mA
I
OUT
≤
7.8 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= V
IL
or V
IH
I
OUT
≤
20
µA
V
IN
= V
IL
or V
IH
I
OUT
≤
6.0 mA
I
OUT
≤7.8
mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum Three State
Leakage Current
V
IN
=V
CC
or GND
Output in High-Impedance
State
V
IN
=V
IH
or V
IL
V
OUT
= V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
I
CC
Maximum Quiescent
Supply Current
(per Package)
6.0
4.0
40
160
µA
SLS
System Logic
Semiconductor
SL74HC374
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
Guaranteed Limit
25
°C
to
-55°C
6.0
30
35
125
25
21
150
30
26
150
30
26
75
15
13
10
15
≤85°C
5.0
24
28
155
31
26
190
38
33
190
38
33
95
19
16
10
15
≤125°C
4.0
20
24
190
38
32
225
45
38
225
45
38
110
22
19
10
15
Unit
MHz
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZH
, t
PZL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
34
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
SU
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock to
Data (Figure 3)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
25
°C
to
-55°C
50
10
9
5
5
5
60
12
10
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
75
15
13
1000
500
400
≤125°C
75
15
13
5
5
5
90
18
15
1000
500
400
Unit
ns
t
h
ns
t
w
ns
t
r,
t
f
ns
SLS
System Logic
Semiconductor
SL74HC374
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor
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