Austin Semiconductor, Inc.
256K X 4 VRAM
256K x 4 DRAM
with 512K x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89497
• MIL-STD-883
SMJ44C251B
MT42C4256
PIN ASSIGNMENT
(Top View)
VRAM
28-Pin DIP (C)
(400 MIL)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
28-Pin SOJ (DCJ)
28-Pin LCC (EC)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
FEATURES
•
Class B High-Reliability Processing
•
DRAM: 262144 Words × 4 Bits
SAM: 512 Words × 4 Bits
•
Single 5-V Power Supply (±10% Tolerance)
•
Dual Port Accessibility–Simultaneous and Asynchronous Access
From the DRAM and SAM Ports
•
Bidirectional-Data-Transfer Function Between the DRAM and the
Serial-Data Register
•
4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many
as Four Memory Address Locations Written per Cycle From an
On-Chip Color Register
•
Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
•
Enhanced Page-Mode Operation for Faster Access
•
CAS-Before-RAS (CBR) and Hidden Refresh Modes
•
All Inputs/Outputs and Clocks Are TTL Compatible
•
Long Refresh Period: Every 8 ms (Max)
•
Up to 33-MHz Uninterrupted Serial-Data Streams
•
3-State Serial I/Os Allow Easy Multiplexing of Video-Data
Streams
•
512 Selectable Serial-Register Starting
•
Split Serial-Data Register for Simplified Real-Time Register Reload
28-Pin ZIP (CZ)
DSF
DQ3
SDQ2
Vss
SDQ0
TRG\
DQ1
GND
A8
A5
Vcc
A3
A1
QSF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
DQ2
SE\
SDQ3
SC
SDQ1
DQ0
W\
RAS\
A8
A4
A7
A2
A0
CAS\
28-Pin FP (F)
SC
SDQ1
SDQ2
TR\/OE\
DQ1
DQ2
ME\/WE\
NC
RAS\
A8
A6
A5
A4
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
OPTIONS
• Timing
100ns, 30ns/27ns
120ns, 35ns/35ns
• Package(s)
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
Ceramic ZIP
Ceramic LCC
MARKING
-10
-12
MT Prefix
DCJ
C
EC
F
CZ
---
SMJ Prefix
---
JDM
HMM
---
SVM
HJM
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN NAME
PIN NAME
(SMJ)
(MT)
A0 - A8
A0 - A8
CAS\
CAS\
DQ0 - DQ3
DQ1 - DQ4
SE\
SE\
RAS\
RAS\
SC
SC
SDQ0 - SDQ3 SDQ1 - SDQ4
TRG\
TR\ /OE\
W\
ME\ /WE\
DSF
DSF
QSF
QSF
Vcc
Vcc
Vss
Vss
GND
NC
DESCRIPTION
Address Inputs
Column Enable
DRAM Data In-Out/Write-Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/Q Output Enable
Write-Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5V Supply
Ground
Ground (Important: Not Connected to
internal Vss, Pin should be left open or
tied to ground.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
DESCRIPTION
The SMJ44C251B/MT42C4256 multiport video RAM is a
high-speed, dual-ported memory device. It consists of a
dynamic random-access memory (DRAM) organized as 262144
words of 4 bits each interfaced to a serial-data register or serial-
access memory (SAM) organized as 512 words of 4 bits each.
The SMJ44C251B/MT42C4256 supports three types of
operation: random access to and from the DRAM, serial access
to and from the serial register, and bidirectional transfer of data
between any row in the DRAM and the serial register. Except
during transfer operations, the SMJ44C251B/MT42C4256 can
be accessed simultaneously and asynchronously from the
DRAM and SAM ports.
During a transfer operation, the 512 columns of the DRAM
are connected to the 512 positions in the serial data register.
The 512 × 4-bit serial-data register can be loaded from the
memory row (transfer read), or the contents of the 512 × 4-bit
serial-data register can be written to the memory row (transfer
write).
The SMJ44C251B/MT42C4256 is equipped with several
features designed to provide higher system-level bandwidth
and to simplify design integration on both the DRAM and SAM
ports. On the DRAM port, greater pixel draw rates can be
achieved by the device’s 4 × 4 block-write mode. The block-
write mode allows four bits of data (present in an on-chip color-
data register) to be written to any combination of four adjacent
column-address locations. As many as 16 bits of data can be
written to memory during each CAS cycle time. Also on the
DRAM port, a write mask or a write-per-bit feature allows mask-
ing any combination of the four input/outputs on any write
cycle. The persistent write-per-bit feature uses a mask register
that, once loaded, can be used on subsequent write cycles. The
mask register eliminates having to provide mask data on every
mask-write cycle.
The SMJ44C251B/MT42C4256 offers a split-register
transfer read (DRAM to SAM) feature for the serial tester (SAM
port). This feature enables real-time register reload
implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high
SMJ44C251B
MT42C4256
VRAM
half and a low half. While one half is being read out of the SAM
port, the other half can be loaded from the memory array. For
applications not requiring real-time register reload (for example,
reloads done during CRT retrace periods), the single-register
mode of operation is retained to simplify design. The SAM can
also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is
loaded, its contents can be transferred to the corresponding
column positions in any row in memory in a single memory
cycle.
The SAM port is designed for maximum performance. Data
can be input to or accessed from the SAM at serial rates up to
33 MHz. During the split-register mode of operation, internal
circuitry detects when the last bit position is accessed from the
active half of the register and immediately transfers control to
the opposite half. A separate output, QSF, is included to
indicate which half of the serial register is active at any given
time in the split-register mode.
All inputs, outputs, and clock signals on the SMJ44C251B/
MT42C4256 are compatible with Series 54 TTL devices. All ad-
dress lines and data-in lines are latched on-chip to simplify
system design. All data-out lines are unlatched to allow greater
system flexibility.
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. The time for row-address setup,
row-address hold, and address multiplex is eliminated, and a
memory cycle time reduction of up to 3× can be achieved,
compared to minimum RAS cycle times. The maximum number
of columns that can be accessed is determined by the maximum
RAS low time and page-mode cycle time used. The
SMJ44C251B/MT42C4256 allows a full page (512 cycles) of
information to be accessed in read, write, or read-modify-write
mode during a single RAS-low period using relatively conser-
vative page-mode cycle times.
The SMJ44C251B/MT42C4256 employs state-of-the-art
technology for very high performance combined with improved
reliability.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
SMJ44C251B
MT42C4256
VRAM
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Austin Semiconductor, Inc.
FUNCTION TABLE
RAS\ FALL
FUNCTION
CAS\
CBR Refresh
Register-to-memory transfer
(transfer write)
Alternate transfer write
(independent of SE\)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(transfer read)
Split-register-transfer read
(must reload tap)
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
Load color register
L
H
H
H
H
H
H
H
H
H
H
H
H
H
TRG\
X
L
L
L
L
L
L
H
H
H
H
H
H
H
W\
X
L
L
L
H
H
L
L
L
L
H
H
H
H
1
SMJ44C251B
MT42C4256
CAS\
FALL
VRAM
ADDRESS
RAS\
CAS\
DQ0 - DQ3
RAS\ CAS\
W\
X
X
X
X
X
X
X
DQ
Mask
DQ
Mask
X
X
X
X
X
X
X
X
X
X
X
Valid
Data
Col
Mask
Valid
Data
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
2
TYPE
R
T
T
T
T
T
R
R
R
R
R
R
R
R
3
DSF
X
X
H
L
L
H
L
L
H
H
L
L
H
H
SE\
X
L
X
H
X
X
X
X
X
X
X
X
X
X
DSF
X
X
X
X
X
X
L
H
L
H
L
H
L
H
X
X
Row
Tap
Addr
Point
Row
Tap
Addr
Point
Refresh
Tap
Addr
Point
Row
Tap
Addr
Point
Row
Tap
Addr
Point
Row
Col
Addr
Addr
Row Blk Addr
Addr
A2-A8
Row
Col
Addr
Addr
Row Blk Addr
A2-A8
Addr
Row
Col
Addr
Addr
Row Blk Addr
A2-A8
Addr
Refresh
X
Addr
Refresh
X
Addr
NOTES:
1. In persistent write-per-bit function, W\ must be high during the refresh cycle.
2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled.
3. R = random access operation, T = transfer operation.
LEGEND
H = HIGH
L = LOW
X = Don’t Care
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
PIN
A0 - A8
CAS\
DQi
DSF
RAS\
SE\
SC
SDQ
TRG\
W\
QSF
NC/GND
Vcc
Vss
Make no external connection or tie
to system Vss
5V supply (typical)
Device ground
DRAM
Row, column address
Column enable, output enable
DRAM data I/O, write mask bits
Block-write enable
Persistent write-per-bit enable
Color-register load enable
Row enable
TRANSFER
Row, tap address
Tap-address strobe
Split-register enable
Alternative write-transfer enable
Row enable
Serial-in mode enable
SMJ44C251B
MT42C4256
SAM
VRAM
DETAILED SIGNAL DESCRIPTION VS. OPERATIONAL MODE
Serial enable
Serial clock
Serial-data I/O
Q output enable
Write enable, write-per-bit select
Transfer enable
Transfer-write enable
Split register
Active status
OPERATION
Depending on the type of operation chosen, the signals of
the SMJ44C251B/MT42C4256 perform different functions. The
“Detailed Signal Description vs. Operational Mode” table
summarizes the signal descriptions and the operational modes
they control.
The SMJ44C251B/MT42C4256 has three kinds of
operations: random-access operations typical of a DRAM,
transfer operations from memory arrays to the SAM, and serial-
access operations through the SAM port. The signals used to
control these operations are described here, followed by
discussions of the operations themselves.
ADDRESS (A0–A8)
For DRAM operation, 18 address bits are required to
decode one of the 262144 storage cell locations. Nine row-
address bits are set up on A0–A8 and latched onto the chip on
the falling edge of RAS\. Nine column-address bits are set up
on A0–A8 and latched onto the chip on the falling edge of
CAS\. All addresses must be stable on or before the falling
edges of RAS\ and CAS\.
During the transfer operation, the states of A0–A8 are
latched on the falling edge of RAS\ to select one of the 512
rows where the transfer occurs. To select one of 512 tap points
(starting positions) for the serial-data input or output, the
appropriate 9-bit column address (A0–A8) must be valid when
CAS\ falls.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
ROW-ADDRESS STROBE (RAS\)
RAS\ is similar to a chip enable because all DRAM cycles
and transfer cycles are initiated by the falling edge of RAS\.
RAS\ is a control input that latches the states of row address,
W\, TRG\, SE\, CAS\, and DSF onto the chip to invoke DRAM
and transfer functions.
COLUMN-ADDRESS STROBE (CAS\)
CAS\ is a control input that latches the states of column
address and DSF to control DRAM and transfer functions.
When CAS\ is brought low during a transfer cycle, it latches
the new tap point for the serial-data input or output. CAS\ also
acts as an output enable for the DRAM outputs DQ0–DQ3.
OUTPUT ENABLE/TRANSFER SELECT (TRG\)
TRG\ selects either DRAM or transfer operation as RAS\
falls. For DRAM operation, TRG\ must be held high as RAS\
falls. During DRAM operation, TRG\ functions as an output
enable for the DRAM outputs DQ0–DQ3. For transfer
operation, TRG\ must be brought low before RAS\ falls.
WRITE-MASK SELECT, WRITE ENABLE (W\)
In DRAM operation, W\ enables data to be written to the
DRAM. W\ is also used to select the DRAM write-per-bit mode.
Holding W\ low on the falling edge of RAS\ invokes the write-
per-bit operation. The SMJ44C251B/MT42C4256 supports both
the normal write-per-bit mode and the persistent write-per-bit
mode.
CONTINUED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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