ER3105DI datasheet, PDF - EEWORLD Datasheet

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ER3105DI: Descriptionvoltage regulators - switching regulators 500ma step-down w/ int mosfets; Categorysemiconductor Other integrated circuit (IC); File Size3MB，25 Pages; ManufacturerENPIRION; Websitehttp://www.enpirion.com/; Environmental Compliance

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voltage regulators - switching regulators 500ma step-down w/ int mosfets

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Enpirion

Power Datasheet

ER3105DI 500mA Wide V

Synchronous Buck Regulator

DS-1041

Datasheet

The Altera® Enpirion® ER3105DI is a 500mA Synchronous

buck regulator with an input range of 3V to 36V. It provides an

easy to use, high efficiency low BOM count solution for a

variety of applications.

The ER3105DI integrates both high-side and low-side NMOS

FET's and features a PFM mode for improved efficiency at

light loads. This feature can be disabled if forced PWM mode

is desired. The part switches at a default frequency of 500kHz

but may also be programmed using an external resistor from

300kHz to 2MHz. The ER3105DI has the ability to utilize

internal or external compensation. By integrating both NMOS

devices and providing internal configuration options, minimal

external components are required, reducing BOM count and

complexity of design.

With the wide V

range and reduced BOM the part provides

an easy to implement design solution for a variety of

applications while giving superior performance. It provides a

very robust design for industrial, battery, and FPGA power

applications.

The part is available in a small Pb free 4mmx3mm DFN

plastic package with an operation temperature range of

-40°C to +125°C

Features

• Wide input voltage range 3V to 36V

• Synchronous Operation for high efficiency

• No compensation required

• Integrated High-side and Low-side NMOS devices

• Selectable PFM or forced PWM mode at light loads

• Internal fixed (500kHz) or adjustable Switching frequency

300kHz to 2MHz

• Continuous output current up to 500mA

• Internal or external Soft-start

• Minimal external components required

• Power-good and enable functions available.

Applications

• FPGA power

• Digital processor power

• Mixed-signal ASIC power

• Industrial control

• Medical devices

• Portable instrumentation

• Distributed Power supplies

• Cloud Infrastructure

100

FSW

= 15V

= 12V

= 5V

EFFICIENCY (%)

CFB

= 24V

= 33V

SYNC

BOOT

GND

PVIN

COMP

CBOOT

100nF

CVIN

10µF

VOUT

COUT

10µF

22µH

AVINO

CAVINO

1µF

POK

PGND

INTERNAL DEFAULT PARAMETER SELECTION

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

OUTPUT LOAD (A)

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. EFFICIENCY vs LOAD, PFM, V

OUT

= 3.3V

101 Innovation Drive

San Jose, CA 95134

www.altera.com

QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in

other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no

responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed

to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

ISO

9001:2008

Registered

March 2014

Altera Corporation

09616

March 14, 2014

Rev A

Page 3

Pin Configuration

ER3105DI

(12 LD 4X3 DFN)

TOP VIEW

SS 1

SYNC 2

BOOT 3

PVIN 4

SW 5

PGND 6

GND

12 FSW

11 COMP

10 FB

AVINO

POK

Pin Descriptions

PIN NUMBER

SYMBOL

PIN DESCRIPTION

The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground

determines the output ramp rate. See “Soft Start” on page 16 for soft-start details. If the SS pin is tied

to AVINO, an internal soft-start of 2ms will be used.

Synchronization and light load operational mode selection input. Connect to logic high or AVINO for

PWM mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to

automatically choose PFM or PWM operation. Connect to an external clock source for synchronization

with positive edge trigger. Sync source must be higher than the programmed IC frequency. There is an

internal 5M pull-down resistor to prevent an undefined logic state if SYNC is left floating.

Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the

necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor

from this pin to SW.

The input supply for the power stage of the regulator and the source for the internal linear bias

regulator. Place a minimum of 4.7µF ceramic capacitance from PVIN to GND and close to the IC for

decoupling.

Switch node output. It connects the switching FET’s with the external output inductor.

Power ground connection. Connect directly to the system GND plane.

Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground.

When the voltage on this pin rises above 1V, the chip is enabled. Connect this pin to PVIN for

automatic start-up. Do not connect EN pin to AVINO since the LDO is controlled by EN voltage.

Open drain power-good output that is pulled to ground when the output voltage is below regulation

limits or during the soft-start interval. There is an internal 5M internal pull-up resistor.

Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the

pin.

Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is

the output of the error amplifier. The output voltage is set by an external resistor divider connected to

FB. In addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator

output voltage.

COMP is the output of the error amplifier. When it is tied to AVINO, internal compensation is used.

When only an RC network is connected from COMP to GND, external compensation is used. See

“Loop Compensation Design” on page 21 for more details.

Frequency selection pin. Tie to AVINO for 500kHz switching frequency. Connect a resistor to GND

for adjustable frequency from 300kHz to 2MHz.

Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage

levels are measured with respect to this pin. The EPAD MUST not float.

SYNC

BOOT

PVIN

PGND

POK

AVINO

COMP

EPAD

FSW

GND

March 2014

Altera Corporation

ER3105DI 500mA Wide VIN Synchronous Buck Regulator

09616

March 14, 2014

Rev A

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