Impala Linear Corporation
ILC5061
SOT-23 Power Supply reset Monitor
General Description
All-CMOS Monitor circuits in a 3-lead SOT-23 package offer the
best performance in power consumption and accuracy.
The ILC5061 comes in a series of ±1% accurate trip voltages to
fit most microprocessor applications. Even though its output
can sink 2mA, the device draws only 1µA in normal operation.
Additionally, a built-in hysteresis of 5% of detect voltage
simplifies system design.
•
•
•
•
•
•
Features
All-CMOS design in SOT-23 and SOT-89 package
±1% precision in Reset Detection
Only 1µA of Iq
2mA of sink current capability
Built-in hysteresis of 5% of detection voltage
Voltage options of 2.6, 2.9, 3.1, 4.4, and 4.6V fit most
supervisory applications
Applications
•
•
•
•
Microprocessor reset circuits
Memory battery back-up circuitry
Power-on reset circuits
Portable and battery powered electronics
Block Diagram
V
IN
V
OUT
V
R E F
V
SS
N-Channel Open Drain Output
Pin Package Configurations
V
I N
2
Ordering Information*
ILC5061AM-26 2.6V+1% Monitor in SOT-23
ILC5061AM-27 2.7V+1% Monitor in SOT-23
ILC5061AM-28 2.8V+1% Monitor in SOT-23
ILC5061AM-29 2.9V+1% Monitor in SOT-23
ILC5061AM-31 3.1V+1% Monitor in SOT-23
ILC5061AM-44 4.4V+1% Monitor in SOT-23
ILC5061AM-46 4.6V+1% Monitor in SOT-23
ILC5061M-26
2.6V+2% Monitor in SOT-23
ILC5061M-27
2.7V+2% Monitor in SOT-23
ILC5061M-28
2.8V+2% Monitor in SOT-23
ILC5061M-29
2.9V+2% Monitor in SOT-23
ILC5061M-31
3.1V+2% Monitor in SOT-23
ILC5061M-44
4.4V+2% Monitor in SOT-23
ILC5061M-46
4.6V+2% Monitor in SOT-23
* Standard product offering comes in tape and reel,
quantity 3000 per reel orientation right
SOT -23
(TOP VI EW)
1
3
V
OUT
V
S S
Impala Linear Corporation
ILC5061 1.7
(408) 574-3939
www.impalalinear.com
June 1999
1
SOT-23 Power Supply reset Monitor
Absolute Maximum Ratings (T
A
=25
ο
C)
Parameter
Input Voltages
Output Current
Output Voltages
Continuous Total
SOT-23
Power Dissipation
Operation Ambient temperature
Storage Temperature
Symbol
V
IN
I
OUT
V
OUT
P
d
T
opr
T
stg
Ratings
12
50
V
SS
-0.3~+V
IN
+03
150
-30~+80
-40~+125
Units
V
mA
V
mW
o
o
C
C
Electrical Characteristics (T
A
=25
ο
C)
Parameter
Detect Fail Voltage
Detect Fail Voltage
Hysteresis Range
Symbol
V
DF
V
DF
V
HYS
Conditions
A grade
Standard grade
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
DF
= 2.1~ 6.0V
N-ch V
DS
= 0.5V
V
IN
= 1.0V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
P-ch V
DS
= 2.1V
V
IN
= 8V
o
30 C <T
opr
<80
o
C
Min
V
DF
X 0.99
V
DF
X 0.99
V
DF
X 0.02
Type
V
DF
V
DF
V
DF
X 0.05
0.9
1.0
1.3
1.6
2.0
Max
V
DF
X 1.01
V
DF
X 1.02
V
DF
X 0.08
2.6
3.0
3.4
3.8
4.2
10.0
Units
V
V
V
!
!
"A
Supply Current
I
SS
Operating Voltage
V
IN
1.5
2.2
7.7
10.1
11.5
13.0
-10
+100
V
Output Current
I
OUT
mA
Temperature
Characteristics
Delay Time Release
Voltage
Output
Inversion)
Note:
#V
DF
/(#T
opr
!
V
DF
)
T
DLY
(V
DR
V
OUT
inversion)
Ppm/
o
C
0.2
ms
1. An additional resistor between the V
IN
pin and supply voltage may cause deterioration of the characteristics due to increasing V
DR
.
Impala Linear Corporation
ILC5061 1.7
(408) 574-3939
www.impalalinear.com
June 1999
2
SOT-23 Power Supply reset Monitor
Functional Description
The following designators
1~6
refer to the timing diagram below.
1.
While the input voltage (V
IN
) is higher than the detect volt-
age (V
DF
), the V
OUT
output pin is at high impedance state.
2.
When the input VIN voltage falls lower than V
DF
, V
OUT
drops near to ground voltage
3.
If the input voltage further decreases below the mini-
mum operating voltage (V
MIN
), the V
OUT
output becomes
unstable. In this condition, if the V
OUT
pin is pulled up,
V
OUT
indicates the V
IN
voltage.
4.
During an increase of the input voltage from the V
SS
voltage, V
OUT
is not stable in the voltage below the V
MIN
.
Exceeding that level, the output stays at the ground level
(V
SS
) between the minimum operating voltage (V
MIN
) and
the detect release voltage (V
DR
).
5.
If the input voltage increases more than V
DR
, then the
V
OUT
output pin is at high impedance state.
6.
The difference between VDR and VDF is the hysteresis
in the system.
Timing Diagram
INPUT VOLTAGE (V
IN
)
DETECT RELEASE VOLTAGE (V
DR
)
6
DETECT FAIL VOLTAGE (V
DF
)
MINIMUM OPERATING VOLTAGE (V
MIN
)
GROUND VOLTAGE (V
SS
)
OUTPUT VOLTAGE (V
OUT
)
GROUND VOLTAGE (V
SS
)
1
2
3
4
5
Impala Linear Corporation
ILC5061 1.7
(408) 574-3939
www.impalalinear.com
June 1999
3
SOT-23 Power Supply reset Monitor
Typical Performance Characteristics - general conditions for all curves
OUTPUT VOLTAGE vs OUTPUT CURRENT
80
OUTPUT VOLTAGE vs OUTPUT CURRENT
ILC5061
10 00
ILC5061
V
I N
=4.0 V
OUTPUT CUR RENT I
O UT
(mA)
OUTPUT CUR RENT I
O UT
(µA)
70
60
50
800
V
I N
=0.8 V
3 .5 V
3.0 V
40
2.5 V
30
20
10
0
0
1
2
3
4
2.0V
600
400
V
I N
=0.7 V
200
1.5V
0.0
0. 0
0. 2
0. 4
0 .6
0. 8
1. 0
OUTPUT V OLTA GE V
O UT
(V)
OU TPU T VOLTAGE V
O UT
(V)
I
D D
vs INPUT VOLTAGE *
4. 0
OUTPUT CURRENT vs INPUT VOLTAGE
25
ILC5061
OU TPU T C URREN T I
OU T
(mA)
ILC5061
V
DS
=0.5V
V
DS = 0.5V
T
o p r
=3 0°C
20
3. 0
T
o p r
=80°C
I
DD
(µA)
15
80 °C
10
25 °C
5
2. 0
25°C
1. 0
-3 0°C
0
0
1
2
3
4
5
6
7
8
9
10
0
0
1
2
3
4
5
INPUT VOLTAGE V
I N
(V )
INPUT VOLTAGE V
I N
(V )
* A spike of ½ to 1
µA
may appear as Vin crosses V
DR
or V
DF
Impala Linear Corporation
ILC5061 1.7
(408) 574-3939
www.impalalinear.com
June 1999
4
XuanTie RISC-V Activity Zone
京公网安备 11010802033920号
EEWORLD
