PO49FCT3802A
3.3V 1:5 CMOS Clock Buffered Driver
1GHz TTL/CMOS Potato Chip
08/03/06
FEATURES:
. Patented technology
. Max input frequency > 1GHz
. Operating frequency up to 1GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 450MHz with 15pf load
. Operating frequency up to 130MHz with 50pf load
. Very low output pin to pin skew < 100ps
. Very low pulse skew < 130ps
. VCC = 1.65V to 3.6V
. Propagation delay < 1.6ns max with 15pf load
. Low input capacitance: 3pf typical
. 1:5 fanout
. Available in 16pin 150mil wide QSOP package
. Available in 16pin 173mil wide TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO49FCT3802A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
TTL output frequency with less than 100ps
output pin to pin skew.
PO49FCT3802A is a 3.3V CMOS 1 input to 5
outputs Buffered driver to achieve 1GHz output
frequency. Typical applications are clock and
signal distribution.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
Logic Block Diagram
Pin Description
Pin Name
INA
O1 to O5
Description
Input
Outputs
1
Copyright
© 2005-2006, Potato Semiconductor Corporation
PO49FCT3802A
3.3V 1:5 CMOS Clock Buffered Driver
1GHz TTL/CMOS Potato Chip
08/02/06
Maximum Ratings
Description
Storage Temperature
Operation Temperature
Operation Voltage
Input Voltage
Output Voltage
Max
-65 to 150
-40 to 85
-0.5 to +4.6
-0.5 to +5.5
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum
Ratings
may
cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
Output High voltage
Output Low voltage
Input High voltage
Input Low voltage
Input High current
Input Low current
Clamp diode voltage
Test Conditions
Vcc=3V Vin=V
IH
or V
IL
, I
OH
= -12mA
Vcc=3V Vin=V
IH
or V
IL
, I
OH
=12mA
Guaranteed Logic HIGH Level (Input Pin)
Guaranteed Logic LOW Level (Input Pin)
Vcc = 3.6V and Vin = 5.5V
Vcc = 3.6V and Vin = 0V
Vcc = Min. And
I
IN
= -18mA
Min
Typ
Max
Unit
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
V
IK
Notes:
1.
2.
3.
4.
5.
2.4
-
2
-0.5
-
-
-
3
0.3
-
-
-
-
-0.7
-
0.5
Vcc
0.8
1
-1
-1.2
V
V
V
V
uA
uA
V
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25
°C
ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
VoH = Vcc – 0.6V at rated current
2
Copyright
© 2005, Potato Semiconductor Corporation
PO49FCT3802A
3.3V 1:5 CMOS Clock Buffered Driver
1GHz TTL/CMOS Potato Chip
09/22/06
Power Supply Characteristics
Symbol
Description
Quiescent Power Supply Current
Test Conditions (1)
Vcc=Max, Vin=Vcc or GND
Min
Typ
Max
Unit
Icc
Q
Notes:
1.
2.
3.
4.
-
0.1
50
uA
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 3.3V, 25°C ambient.
This parameter is guaranteed but not tested.
Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
Capacitance
Parameters (1)
Description
Input Capacitance
Output Capacitance
Test Conditions
Vin = 0V
Vout = 0V
Typ
Max
Unit
Cin
Cout
Notes:
3
-
4
6
pF
pF
1 This parameter is determined by device characterization but not production tested.
Switching Characteristics
Symbol
Description
Propagation Delay A to Bn
Propagation Delay A to Bn
Rise/Fall Time
Pulse Skew (Same Package)
Output Pin to Pin Skew (Same Package)
Output Skew (Different Package)
Input Frequency
Input Frequency
Input Frequency
Input Frequency
Test Conditions (1)
CL = 15pF
CL = 15pF
0.8V – 2.0V
CL = 15pF, 125MHz
CL = 15pF, 125MHz
CL = 15pF, 125MHz
CL = 5 0 p F
CL =15pF
CL = 5pF
CL = 2pF
M ax
Unit
t
PLH
t
PHL
tr/tf
tsk(p)
tsk(o)
tsk(pp)
fmax
fmax
fmax
fmax
Notes:
1.6
1.6
0.8
0.1
0.13
0.4
130
450
700
1000
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
3
Copyright
© 2005, Potato Semiconductor Corporation
PO49FCT3802A
3.3V 1:5 CMOS Clock Buffered Driver
1GHz TTL/CMOS Potato Chip
11/22/05
Test Waveforms
Test Circuit
50
Ω
4
Copyright
© 2005, Potato Semiconductor Corporation
PO49FCT3802A
3.3V 1:5 CMOS Clock Buffered Driver
1GHz TTL/CMOS Potato Chip
11/22/05
Packaging Mechanical Drawing: 16 pin QSOP
Packaging Mechanical Drawing: 16 pin TSSOP
5
Copyright
© 2005, Potato Semiconductor Corporation
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