EDI88128C
128KX8 MONOLITHIC SRAM, SMD 5962-89598
n
Access Times of 70, 85, 100ns
n
Available with Single Chip Selects (EDI88128) or Dual
Chip Selects (EDI88130)
n
2V Data Retention (LP Versions)
n
CS and OE Functions for Bus Control
n
TTL Compatible Inputs and Outputs
n
Fully Static, No Clocks
n
Organized as 128Kx8
n
Industrial, Military and Commercial Temperature Ranges
n
Thru-hole and Surface Mount Packages JEDEC Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
n
Single +5V (±10%) Supply Operation
FEATURES
The EDI88128C is a high speed, high performance, Mono-
lithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional
chip select line (CS2) which will automatically power down
the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in memory
banking where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional
input-output lines to provide simultaneous access to all
bits in a word. An automatic power down feature permits
the on-chip circuitry to enter a very low standby mode and
be brought back into operation at a speed equal to the
address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a
2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
F
IG
. 1
P
IN
C
ONFIGURATION
P D
IN
ESCRIPTION
32 DIP
32 SOJ
I/O
0-7
A
0-16
WE
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
T
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
AØ
I/OØ
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OP
V
IEW
CS
1
, CS
2
32 V
CC
31 A15
30 NC/CS2*
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
OE
V
CC
V
SS
NC
B
LOCK
D
IAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
1
March 2002 Rev. 16
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
A
Parameter
BSOLUTE
M
AXIMUM
R
ATINGS
T
Unit
O
E
CS
RUTH
T
ABLE
1
CS
2
WE
Mode
Output
Power
Voltage on any pin relative to Vss
Operating T
emperature T
-0.5 to 7.0
V
A
(Ambient)
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
20
175
°C
°C
°C
°C
W
mA
°C
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
X
X
X
H
L
X
H
X
X
L
L
L
X
L
L
H
H
H
X
X
X
H
H
L
Standby
Standby
Output Deselect
Output Deselect
Read
Write
High Z
High Z
High Z
High Z
Data Out
Data In
Icc
2
, Icc
3
Icc
2
, Icc
3
Icc
1
Icc
1
Icc
1
Icc
1
R
Parameter
ECOMMENDED
O
PERATING
C
ONDITIONS
Symbol
Min
T
yp
Max
Unit
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extended periods may affect
reliability.
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.2
-0.3
5.0
0
—
—
5.5
0
Vcc +0.5
+0.8
V
V
V
V
C
(TA = +25°C)
APACITANCE
Parameter
Symbol
Condition
Max
Unit
Address Lines
Input/Output Lines
C
I
C
O
V
IN
= Vcc or Vss, f = 1.0MHz
V
OUT
= Vcc or Vss, f = 1.0MHz
12
14
pF
pF
These parameters are sampled, not 100% tested.
DC C
(V
CC
= 5V, T
A
= -55°C
Parameter
Symbol
Conditions
HARACTERISTICS
TO
+125°C)
Units
Min
Typ
Max
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
, CS
1
³
V
IH
and/or CS
2
£
V
IL
WE, CS
1
= V
IL
, I
I/O
= 0mA, Min Cycle
CS
2
= V
IH
CS
1
³
V
IH
and/or CS
2
£
V
IL
, V
IN
³
V
IH
or
£
V
IL
CS
1
³
V
CC
-0.2V and/or CS
2
£
Vcc +0.2V
V
IN
³
Vcc -0.2V or V
IN
£
0.2V
I
OL
= 2.1mA
I
OH
= -1.0mA
C
LP
(70-85ns)
(100ns)
-5
-10
—
—
—
—
—
—
2.4
—
—
+5
+10
120
110
10
µA
µA
mA
mA
mA
mA
mA
V
V
1
—
—
—
5
1
0.4
—
NOTE: DC test conditions : V
IL
= 0.3V, V
IH
= Vcc -0.3V
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
EDI88128C
AC C
R
C
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
HARACTERISTICS
EAD
Symbol
Parameter
JEDEC
Alt.
Min
70ns
Max
Min
YCLE
TO
+125°C)
85ns
Max
Min
100ns
Max
Units
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z (1)
Chip Disable to Output in High Z (1)
OutputHoldfromAddressChange
OutputEnabletoOutputValid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z (1)
t
AVAV
t
AVQV
t
ELQV
t
SHQV
t
ELQX
t
SHQX
t
EHQZ
t
SLQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
ACS
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
70
70
70
70
3
3
0
0
3
25
0
0
30
30
30
85
85
85
85
3
3
0
0
3
30
0
0
30
30
30
100
100
100
100
3
3
0
0
3
50
0
0
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC T
EST
C
ONDITIONS
Figure 1
Vcc
Figure 2
Vcc
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
480Ω
V
SS
to 3.0V
5ns
1.5V
Figure 1
480Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88128C
AC C
W
C
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
HARACTERISTICS
RITE
Symbol
Parameter
JEDEC
Alt.
Min
70ns
Max
Min
YCLE
TO
+125°C)
85ns
Max
Min
100ns
Max
Units
Write Cycle Time
Chip Select to End of Write
t
AVAV
t
ELWH
t
ELEH
t
SHWH
t
SHSL
t
AVWL
t
AVEL
t
AVSH
t
AVWH
t
WLWH
t
WLEH
t
WLSL
t
WHAX
t
EHAX
t
SLAX
t
WHDX
t
EHDX
t
SLDX
t
WLQZ
t
DVWH
t
DVEH
t
DVSL
t
WHQX
t
WC
t
CW
t
CW
t
CW
t
CW
t
AS
t
AS
t
AS
t
AW
t
WP
t
WP
t
WP
t
WR
t
WR
t
WR
t
DH
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
DW
t
WLZ
70
60
60
60
60
0
0
0
60
35
35
35
5
5
5
0
0
0
0
35
35
35
5
30
85
75
75
75
75
0
0
0
75
70
70
70
5
5
5
0
0
0
0
40
40
40
5
35
100
85
85
85
85
0
0
0
85
80
80
80
5
5
5
0
0
0
0
40
40
40
5
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
EDI88128C
F .2T
IG
IMING
W
AVEFORM
-R
EAD
C
YCLE
t
AVAV
ADDRESS
t
AVQV
CS
1
t
ELQV
t
ELQX
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
t
EHQZ
CS
2
t
SHQV
t
SHQX
OE
t
SLQZ
t
AVQV
DATA I/O
t
AVQX
DATA
1
DATA 2
t
GLQV
t
GLQX
DATA I/O
READ CYCLE 2 (WE HIGH)
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
F .3W
IG
RITE
C
YCLE
1
t
AVAV
ADDRESS
t
AVWL
WE
t
AVWH
t
WLWH
t
WHAX
CS
1
t
ELWH
CS
2
t
SHWH
DATA IN
t
DVWH
DATA VALID
t
WHQX
t
WHDX
t
WLQZ
DATA OUT
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
F .4W
IG
RITE
C
YCLE
2
t
AVAV
W
RITE
C
YCLE
3
t
AVAV
t
SLAX
WS32K32-XHX
ADDRESS
ADDRESS
t
AVEL
WE
t
WLEH
t
EHAX
WE
t
AVSH
t
WLSL
t
ELEH
CS
1
CS
1
t
SHSL
CS
2
CS
2
t
DVEH
DATA IN
DATA VALID
t
EHDX
DATA IN
t
DVSL
DATA VALID
t
SLDX
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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