IC89E54/58/64
8-BITS SINGLE MICROCONTROLLER
with 16/32/64-Kbytes of FLASH,
256 byte +512 byte RAM
FEATURES
• 80C52 based architecture
• 256 Byte RAM internal RAM and 512 Bytes
auxiliary RAM available
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Power Save Mode :
GENERAL DESCRIPTION
IC89E54, IC89E58, IC89E64 are members of ICSI
embedded microcontroller family. The IC89E54/58/64 uses
the same powerful instruction set, has the same architecture,
and is pin-to-pin compatible with standard 80C51 controller
devices. They have IC89E54/58/64 all functions and some
enhanced function is included. These enhanced functions
include 512 bytes auxiliary memory, 36 I/O pins (44 pin
package only), 8 interrupts (44 pin package only) with two-
level priority, Power off flag, Low EMI mode, power down
mode is waken up from interrupt level trigger mode.
1) Idle Mode
2) Power Down Mode - waken up from interrupt
level trigger mode
Program memory lock
– Lock bits (3)
Four 8-bit I/O ports, 32 I/O lines
Memory addressing capability
– 64K Program Memory and 64K Data Memory
CMOS and TTL compatible
Maximum speed ranges at Vcc = 5V is 40 MHz
and most instructions execute in 0.3 µs
Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
16K/32K/64K Byte Flash Memory with fast-pulse
programming algorithm
36 I/O pins(above 44-pin package only)
8 interrupts vectors (above 44-pin package
only)
Low EMI mode
•
•
•
•
•
•
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
•
•
•
•
Figure 1. IC89E54/58/64 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
I egr ed C i cui
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MC012-0C 11/16/2001
1
IC89E54/58/64
Table 1. Detailed Pin Description
Symbol
P0.0-P0.7
PDIP
39-32
PLCC
43-36
PQFP
37-30
I/O
I/O
Name and Function
Port 0:
Port 0 is an open-drain, bi-directional I/O port. Port 0 pins
that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.
Port 0 also receives the command and code bytes during
memory program and verification, and outputs the code bytes
during program verification. External pullups are required during
program verification.
Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, port
1 pins that are externally pulled low will source current because
of the internal pullups.
Port 1 also receives the low-order address byte during memory
program and verification.
T2(P1.0) :
Timer/counter 2 external count input.
T2EX(P1.1):
Timer/counter 2 trigger input.
Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally pulled low will source current
because of the internal pullups. Port 2 emits the high order
address byte during fetches from external program memory and
during accesses to external data memory that used 16-bit
addresses. In this application, it uses strong internal pullups
when emitting 1s. During accesses to external data memory that
use 8-bit addresses, port 2 emits the contents of the P2 special
function register.
Port 2 also receives the high-order address bits from A13 to A8
and some control signals during Flash programming and
verification. P2.6, P2.7 are the control signals while the chip
programs and erases. P2.6 is a program command strobe
signal. P2.7 is a data output enable signal.
P1.0-P1.7
1-8
2-9
40-44
I/O
1
2
P2.0-P2.7
21-28
2
3
24-31
40
41
18-25
I
I
I/O
I egr ed C i cui
nt at
r tSol i I
uton nc.
MC012-0C 11/16/2001
5
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