v1.1
ProASIC3 Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
®
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
†
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC
®
3
devices) via JTAG (IEEE 1532–compliant)
†
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
†
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
†
and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
‡
• Programmable Output Slew Rate
†
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase-Shift,
Multiply/Divide,
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Delay
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
Embedded Memory
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Table 1 •
ProASIC3 Product Family
ProASIC3 Devices
A3P015
1
ARM7 Devices
Cortex-M1 Devices
1
System Gates
15 k
Typical Equivalent Macrocells
128
VersaTiles (D-flip-flops)
384
RAM kbits (1,024 bits)
–
4,608-Bit Blocks
–
FlashROM Bits
1k
2
Secure (AES) ISP
–
Integrated PLL in CCCs
–
3
VersaNet Globals
6
I/O Banks
2
Maximum User I/Os
49
Package Pins
QFN
QN68
VQFP
TQFP
PQFP
FBGA
A3P030
A3P060
A3P125
A3P250
M1A3P250
250 k
2,048
6,144
36
8
1k
Yes
1
18
4
157
QN132
5
VQ100
PQ208
FG144/256
5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
A3P400
M1A3P400
400 k
–
9,216
54
12
1k
Yes
1
18
4
194
A3P600
M1A3P600
600 k
–
13,824
108
24
1k
Yes
1
18
4
235
A3P1000
M7A3P1000
M1A3P1000
1M
–
24,576
144
32
1k
Yes
1
18
4
300
30 k
256
768
–
–
1k
–
–
6
2
81
QN48, QN68,
QN132
VQ100
60 k
512
1,536
18
4
1k
Yes
1
18
2
96
QN132
VQ100
TQ144
FG144
125 k
1,024
3,072
36
8
1k
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
Notes:
1. Refer to the
CoreMP7
datasheet or
Cortex-M1
product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
ProASIC3E Flash Family FPGAs
handbook.
5. The M1A3P250 device does not support this package.
† A3P015 and A3P030 devices do not support this feature.
February 2009
© 2009 Actel Corporation
‡ Supported only by A3P015 and A3P030 devices.
I
I/Os Per Package
1
ProASIC3
Devices
ARM7 Devices
Cortex-M1
Devices
M1A3P250
3,6
I/O Type
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
–
–
–
–
35
25
44
74
FG484
23 × 23
529
1.0
2.23
Single-Ended I/O
2
Single-Ended I/O
2
Single-Ended I/O
2
Single-Ended I/O
2
–
–
–
–
154
97
177
300
M1A3P400
3
M1A3P600
A3P015
A3P030
A3P060
A3P125
A3P250
3
A3P400
3
A3P600
A3P1000
M7A3P1000
M1A3P1000
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Package
QN48
QN68
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Notes:
34
49
–
–
–
–
–
–
–
49
81
77
–
–
–
–
–
–
80
71
91
–
96
–
–
–
84
71
100
133
97
–
–
–
87
68
–
151
97
157
–
–
19
13
–
34
24
38
–
–
–
–
–
151
97
178
194
–
–
–
–
34
25
38
38
–
154
97
177
235
–
–
–
–
35
25
43
60
1. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3 Flash Family FPGAs
handbook to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer
to the
ProASIC3 Flash Family FPGAs
handbook for position assignments of the 15 LVPECL pairs.
4. FG256 and FG484 are footprint-compatible packages.
5. "G" indicates RoHS-compliant packages. Refer to
"ProASIC3 Ordering Information" on page III
for the location of the
"G" in the part number.
6. The M1A3P250 device does not support FG256 or QN132 packages.
Table 2 •
ProASIC3 FPGAs Package Sizes Dimensions
Package
Length × Width
(mm\mm)
Nominal Area
(mm
2
)
Pitch (mm)
Height (mm)
QN48
6×6
36
0.4
0.90
QN68
8×8
64
0.4
0.90
QN132
8×8
64
0.5
0.75
VQ100
14 × 14
196
0.5
1.00
TQ144
20 × 20
400
0.5
1.40
PQ208
28 × 28
784
0.5
3.40
FG144
13 × 13
169
1.0
1.45
FG256
17 × 17
289
1.0
1.60
II
Single-Ended I/O
v1.1
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
A3P1000
_
1
FG
G
144
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P015 = 15,000 System Gates
A3P030 = 30,000 System Gates
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P400 = 400,000 System Gates
A3P600 = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
ProASIC3 Devices with ARM7
M7A3P1000 = 1,000,000 System Gates
ProASIC3 Devices with Cortex-M1
M1A3P250 =
M1A3P400 =
M1A3P600 =
M1A3P1000 =
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
*
The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in
the commercial temperature range.
v1.1
III
Temperature Grade Offerings
Package
ARM7 Devices
Cortex-M1 Devices
QN48
QN68
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
–
C, I
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
–
–
–
–
–
–
–
C, I
C, I
C, I
–
C, I
–
–
–
–
C, I
C, I
C, I
C, I
C, I
–
–
M1A3P250
–
–
C, I
C, I
–
C, I
C, I
C, I
–
M1A3P400
–
–
–
–
–
C, I
C, I
C, I
C, I
M1A3P600
–
–
–
–
–
C, I
C, I
C, I
C, I
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
M7A3P1000
M1A3P1000
–
–
–
–
–
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature
3. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start
with M7 (CoreMP7) and M1 (Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
–F
1
Std.
–1
–2
✓
–
✓
✓
✓
✓
✓
✓
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
IV
v1.1
1 – ProASIC3 Device Family Overview
General Description
ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and
features beyond those of the ProASIC
PLUS®
family. Nonvolatile flash technology gives ProASIC3
devices the advantage of being a secure, low-power, single-chip solution that is live at power-up
(LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and
A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates,
supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM7 soft IP core and Cortex-M1 devices. The ARM-enabled devices
have Actel ordering numbers that begin with M7A3P (CoreMP7) and M1A3P (Cortex-M1) and do
not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property (IP) cannot be compromised or
copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3
family device architecture mitigates the need for ASIC migration at higher user volumes. This
makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in
the consumer, networking/ communications, computing, and avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock,
which provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices
can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. The AES standard was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES
decryption engine and a flash-based AES key that make them the most comprehensive
programmable logic device security solution available today. ProASIC3 devices with AES-based
security allow for secure, remote field updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP
thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure
design verification is possible.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the
ARM core must be protected at all times, AES encryption is always on for the core logic, so
bitstreams are always encrypted. There is no user access to encryption for the FlashROM
programming data.
v1.1
1-1
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
